89hpes10t4bg2 Integrated Device Technology, 89hpes10t4bg2 Datasheet - Page 3

• Manufacturer Part Number: 89hpes10t4bg2
• Description: 10-lane 4-port Gen2 Pci Express Switch
• Manufacturer: Integrated Device Technology

3(a), the master and slave SMBuses are tied together and the PES10T4BG2 acts both as a SMBus master as well as a SMBus slave on this bus. This
requires that the SMBus master or processor that has access to PES10T4BG2 registers supports SMBus arbitration. In some systems, this SMBus
master interface may be implemented using general purpose I/O pins on a processor or micro controller, and may not support SMBus arbitration. To
support these systems, the PES10T4BG2 may be configured to operate in a split configuration as shown in Figure 3(b).
The PES10T4BG2 supports reading and writing of the serial EEPROM on the master SMBus via the slave SMBus, allowing in system programming of
the serial EEPROM.
Hot-Plug Interface
PES10T4BG2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following reset
and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES10T4BG2 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES10T4BG2. In response to an I/O expander interrupt, the PES10T4BG2 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
© 2009 Integrated Device Technology, Inc
As shown in Figure 3, the master and slave SMBuses may be used in a unified or split configuration. In the unified configuration, shown in Figure
In the split configuration, the master and slave SMBuses operate as two independent buses and thus multi-master arbitration is never required.
The PES10T4BG2 supports PCI Express Hot-Plug on each downstream port. To reduce the number of pins required on the device, the
The PES10T4BG2 provides 9 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
The following tables list the functions of the pins provided on the PES10T4BG2. Some of the functions listed may be multiplexed onto the same
IDT 89HPES10T4BG2 Data Sheet
Note: In the PES10T4BG2, the three downstream ports are labeled ports 2, 4, and 6.
PES10T4BG2
(a) Unified Configuration and Management Bus
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
*Notice: The information in this document is subject to change without notice
EEPROM
Figure 3 SMBus Interface Configuration Examples
Serial
...
Devices
SMBus
Other
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(b) Split Configuration and Management Buses
PES10T4BG2
MSMBCLK
SSMBCLK
MSMBDAT
SSMBDAT
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
July 1, 2009