89hpes12nt3 Integrated Device Technology, 89hpes12nt3 Datasheet - Page 7

• Manufacturer Part Number: 89hpes12nt3
• Description: 12-lane, 3-port Pcie Inter-domain Switch
• Manufacturer: Integrated Device Technology

IDT 89HPES12NT3 Data Sheet
JTAG_TRST_N
JTAG_TDO
JTAG_TMS
V
Signal
Signal
V
DD
V
V
V
DD
DD
V
TT
DD
CORE
SS
APE
PE
PE
IO
Type
Type
O
I
I
I
I
I
I
I
I
JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Core V
I/O V
PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
PCI Express Termination Power.
Ground.
Table 6 Power and Ground Pins
Table 5 Test Pins (Part 2 of 2)
DD
DD
. LVTTL I/O buffer power supply.
. Power supply for core logic.
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Name/Description
Name/Description
April 11, 2007