89hpes24nt6ag2 Integrated Device Technology, 89hpes24nt6ag2 Datasheet - Page 2

• Manufacturer Part Number: 89hpes24nt6ag2
• Description: 24-lane 6-port Pcie Gen2 System Interconnect Switch With Non-transparent Bridging
• Manufacturer: Integrated Device Technology

IDT 89HPES24NT6AG2 Product Brief
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– Supports 100 MHz and 125 MHz reference clock frequencies
– Flexible port clocking modes
– Hot-plug controller on all ports
– All ports support hot-plug using low-cost external I
– Configurable presence-detect supports card and cable appli-
– GPE output pin for hot-plug event notification
– Hot-swap capable I/O
– Supports D0, D3hot and D3 power management states
– Active State Power Management (ASPM)
– SerDes power savings
– ECRC support
– AER on all ports
– SECDED ECC protection on all internal RAMs
– End-to-end data path parity protection
– Checksum Serial EEPROM content protected
– Ability to generate an interrupt (INTx or MSI) on link up/down
– Supports Root (BIOS, OS, or driver), Serial EEPROM, or
– Common switch configurations are supported with pin strap-
– Supports in-system Serial EEPROM initialization/program-
– Range of 0 to 127.5 degrees Celsius
– Three programmable temperature thresholds with over and
– Automatic recording of maximum high or minimum low
Clocking
Hot-Plug and Hot Swap
Power Management
Reliability, Availability, and Serviceability (RAS)
Initialization / Configuration
On-Die Temperature Sensor
• Common clock
• Non-common clock
• Local port clock with SSC (spread spectrum setting) and port
• Hot-plug supported on all downstream switch ports
• Enables SCI/SMI generation for legacy operating system
• Supports L0, L0s, L1, L2/L3 Ready, and L3 link states
• Configurable L0s and L1 entry timers allow performance/
• Supports low swing / half-swing SerDes operation
• SerDes associated with unused ports are turned off
• SerDes associated with unused lanes are placed in a low
expanders
cations
transitions
SMBus switch initialization
ping (no external components)
ming
under temperature threshold alarms
temperature
reference clock input
support
power-savings tuning
power state
2
C I/O
2 of 7
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– Ability to inject AER errors simplifies in system error handling
– On-chip link activity and status outputs available for several
– Per port link activity and status outputs available using
– Supports IEEE 1149.6 AC JTAG and IEEE 1149.1 JTAG
– PCI Express Base Specification 2.1 compliant
– Implements the following optional PCI Express features
– Requires three power supply voltages (1.0V, 2.5V, and 3.3V)
9 General Purpose I/O
Test and Debug
Standards and Compatibility
Power Supplies
Packaged in a 23mm x 23mm 484-ball Flip Chip BGA with
1mm ball spacing
• Advanced Error Reporting (AER) on all ports
• End-to-End CRC (ECRC)
• Access Control Services (ACS)
• Device Serial Number Enhanced Capability
• Sub-System ID and Sub-System Vendor ID Capability
• Internal Error Reporting
• Multicast
• VGA and ISA enable
• L0s and L1 ASPM
• ARI
software validation
ports
external I
2
C I/O expander for all remaining ports
September 15, 2009