am79c901a Advanced Micro Devices, am79c901a Datasheet - Page 28

• Manufacturer Part Number: am79c901a
• Description: Homephy Single-chip 1/10 Mbps Home Networking Phy
• Manufacturer: Advanced Micro Devices

MII-Compatible Interface for HomePNA
PHY
The control and data signals that are utilized in the MII-
compatible interface of the 1 Mbps HomePNA PHY
function in an manner that is identical to that as defined
in the 802.3u specification. The signals RX_CLK and
TX_CLK function in a slightly different manner in that
they operate at a reduced data rate and that these
clock signals do not run at a constant rate due to the
RLL25™ encoding scheme. See Table 4.
Note: During the AID interval, TX_CLK and RX_CLK
stop for up to 140 s.
Figure 14 and Figure 15 represent the signal relation-
ships when the MII-compatible data interface is utilized.
28
Idle (excluding IPG
time)
Preamble (first 64 bits
of TX MAC frame)
Data (throughout the
data phase)
IPG (96 bit times
following CRS )
SCLK
SDO
SDI
CS
WRITE
READ
Condition
Table 4. MII-Compatible Timing
1
2
PRE
1...1
1...1
3
4
400 ns - 40 s
CLK Period
Op Codes
2333.34 ns
933.33 ns
933.33 ns
ST
01
01
5
6
OP
10
01
7
Table 5. MII Control Frame Format
Error Code = 0
250 kHz avg.
Frequency
Figure 13. Normal Operation
8
428.6 kHz
1.07 MHz
1.07 MHz
P R E L I M I N A R Y
CLK
PHYADD
9
AAAAA
AAAAA
Address
10
Am79C901A
11
12
The signals TX_CLK and RX_CLK will toggle at a rate
of approximately 428 kHz during idle time. When the
TX_EN signal is asserted to indicate the beginning of a
transmission, the clock rate will enter the preamble
phase. Once the SFD has been detected and the
HomePNA PHY has begun the transmission of the
HomePNA header, the clock enters the data phase.
When the TX_EN signal is deasserted to indicate the
ending of a transmission, TX_CLK is halted until the
RXDATA path detects the end of the packet. At this
time, the clock rate is increased to the IPG data rate for
96 bit times and then returns to the Idle state.
MII-Compliant Interface for 10BASE-T PHY
The MII interface is fully IEEE 802.3u-compliant when
the 10BASE-T PHY is selected. The management in-
terface specified in Clause 22 of the IEEE 802.3u stan-
dard provides for a simple two wire, serial interface to
connect a management entity and a managed PHY for
the purpose of controlling the PHY and gathering sta-
tus information. The two lines are Management Data
Input/Output (MDIO) and Management Data Clock
(MDC). A station management entity, which is attached
to multiple PHY entities, must have prior knowledge of
the appropriate PHY address for each PHY entity.
The management interface physically transports man-
is encapsulated in a frame format as specified in
Clause 22 of the IEEE 802.3u standard and is shown
in Table 5.
agement information across the MII. The information
REGADD
RRRRR
RRRRR
13
14
15
16
TA
Z0
10
17
Data Out
Data In
18
D15………D0
D15………D0
19
DATA
30
31
22304B-15
32
IDLE
Z
Z