am79c972b Advanced Micro Devices, am79c972b Datasheet - Page 22

• Manufacturer Part Number: am79c972b
• Description: Pcnet?-fast+ Enhanced 10/100 Mbps Pci Ethernet Controller With Onnow Support
• Manufacturer: Advanced Micro Devices

COL
Collision
COL is an input that indicates that a collision has been
detected on the network medium.
Note: The COL pin is multiplexed with the CLSN pin.
CRS
Carrier Sense
CRS is an input that indicates that a non-idle medium,
due either to transmit or receive activity, has been de-
tected.
Note: The CRS pin is multiplexed with the RXEN pin.
RX_CLK
Receive Clock
RX_CLK is a clock input that provides the timing refer-
ence for the transfer of the RX_DV, RXD[3:0], and
RX_ER signals into the Am79C972 device. RX_CLK
must provide a nibble rate clock (25% of the network
data rate). Hence, an MII transceiver operating at 10
Mbps must provide an RX_CLK frequency of 2.5 MHz
and an MII transceiver operating at 100 Mbps must pro-
vide an RX_CLK frequency of 25 MHz. When the exter-
nal PHY switches the RX_CLK and TX_CLK, it must
provide glitch-free clock pulses.
Note: The RX_CLK pin is multiplexed with the RXCLK
pin.
RXD[3:0]
Receive Data
RXD[3:0] is the nibble-wide MII receive data bus. Data
on RXD[3:0] is sampled on every rising edge of
RX_CLK while RX_DV is asserted. RXD[3:0] is ignored
while RX_DV is de-asserted.
Note: The RXD[0] pin is multiplexed with the
RXFRTGD pin.
If the MII port is not selected, the RXD[3:0] pin can be
left floating.
RX_DV
Receive Data Valid
RX_DV is an input used to indicate that valid received
data is being presented on the RXD[3:0] pins and
RX_CLK is synchronous to the receive data. In order
for a frame to be fully received by the Am79C972 de-
vice on the MII, RX_DV must be asserted prior to the
RX_CLK rising edge, when the first nibble of the Start
of Frame Delimiter is driven on RXD[3:0], and must re-
main asserted until after the rising edge of RX_CLK,
when the last nibble of the CRC is driven on RXD[3:0].
RX_DV must then be deasserted prior to the RX_CLK
22
Input
Input
Input
Input
Input
Am79C972
rising edge which follows this final nibble. RX_DV tran-
sitions are synchronous to RX_CLK rising edges.
Note: The RX_DV pin is multiplexed with the
RXFRTGE pin.
If the MII port is not selected, the RX_DV pin can be left
floating.
RX_ER
Receive Error
RX_ER is an input that indicates that the MII trans-
ceiver device has detected a coding error in the receive
frame currently being transferred on the RXD[3:0] pins.
When RX_ER is asserted while RX_DV is asserted, a
CRC error will be indicated in the receive descriptor for
the incoming receive frame. RX_ER is ignored while
RX_DV is deasserted. Special code groups generated
on RXD while RX_DV is deasserted are ignored (e.g.,
Bad SSD in TX and IDLE in T4). RX_ER transitions are
synchronous to RX_CLK rising edges.
Note: The RX_ER pin is multiplexed with the RXDAT
pin.
MDC
Management Data Clock
MDC is a non-continuous clock output that provides a
timing reference for bits on the MDIO pin. During MII
management port operations, MDC runs at a nominal
frequency of 2.5 MHz. When no management opera-
tions are in progress, MDC is driven LOW. The MDC is
derived from the Time Base Clock.
If the MII port is not selected, the MDC pin can be left
floating.
MDIO
Management Data I/O
MDIO is the bidirectional MII management port data
pin. MDIO is an output during the header portion of the
management frame transfers and during the data por-
tions of write transfers. MDIO is an input during the
data portions of read data transfers. When an operation
is not in progress on the management port, MDIO is not
driven. MDIO transitions from the Am79C972 controller
are synchronous to MDC falling edges.
If the PHY is attached through an MII physical connec-
tor, then the MDIO pin should be externally pulled down
to V
board, then the MDIO pin should be externally pulled
up to V
SS
CC
with a 10-k
with a 10-k
5% resistor. If the PHY is on
5% resistor
Input/Output
Output
Input