am79c989 Advanced Micro Devices, am79c989 Datasheet - Page 15

• Manufacturer Part Number: am79c989
• Description: Quad Ethernet Switching Transceiver
• Manufacturer: Advanced Micro Devices

The QuEST can be manually configured to support
either half-duplex or full-duplex operation. The QuEST
device can operate with any remote 10BASE-T
standard device or like devices that support the Auto-
Negotiation algorithm, including 10/100 Mbps devices.
10BASE-T Algorithm
T h e Q u E S T d ev i c e i m p l e m e n t s t h e s t a n d a r d
10BASE-T algorithm as defined in the IEEE 802.3
specification. The 10BASE-T algorithm uses Normal
Link Pulses (NLP) to establish link integrity. In the stan-
dard 10BASE-T algorithm, link pulses are transmitted
approximately every 16 ms 8 ms in the absence of
transmitted data. Upon reception of five consecutive
link pulses with constant polarity within the specified
minimum and maximum times, the QuEST device will
detect the presence of a valid link. Reception of a valid
receive frame will transition the QuEST device to the
link pass state in the absence of link pulses.
Auto-Negotiation Algorithm
The Auto-Negotiation function determines the abilities
of two networking devices at each end of a physical
link, if both devices are capable of Auto-Negotiation.
After exchanging abilities, the QuEST device and
mote link partner device acknowledge each other and
choose which advertised abilities to support. The Auto-
Negotiation function of the QuEST chip facilitates an
ordered resolution between exchanged abilities. This
exchange allows the devices at either end of the link to
take maximum advantage of their respective shared
abilities. In the case of the QuEST device, the primary
capability it can advertise is full-duplex operation, offer-
ing the potential of a 20-Mbps link instead of 10 Mbps
in half-duplex mode.
The QuEST device implements the transmit and re-
ceive Auto-Negotiation algorithm as defined in IEEE
802.3u standard. The Auto-Negotiation algorithm uses
a burst of link pulses called Fast Link Pulses (FLPs).
The burst of link pulses are spaced between 55 and
140 s so as to be ignored by the standard 10BASE-T
algorithm. The FLP burst conveys information about
the abilities of the sending device. The receiver can ac-
cept and decode an FLP burst to learn the abilities of
the sending device. The link pulses transmitted con-
form to the standard 10BASE-T template.
The QuEST device uses the Auto-Negotiation algo-
rithm to advertise either full- or half-duplex capabilities.
The QuEST device can be programmed to force either
half- or full-duplex, or to auto-negotiate between half-
and full-duplex operation.
The Auto-Negotiation algorithm is initiated when one
of the following events occurs: Reset, Auto-Negotia-
tion reset, transition to link fail state, or the Auto-Ne-
gotiation enable bit is set. After the Auto-Negotiation
algorithm is completed, the device will be in either a
P R E L I M I N A R Y
Am79C989
re-
half- or full-duplex state. The result of the Auto-Nego-
tiation can be read from the status register for the port
of interest. After conclusion of the Auto-Negotiation
process, the QuEST device reverts back to the stan-
dard 10BASE-T link integrity algorithm (i.e., transmis-
sion of standard link pulses).
The QuEST device also supports “Next Page,” offering
the flexibility to add new features in the future.
Manchester Encoder
The QuEST device provides separate Manchester
encode circuits per transmit channel. The QuEST
device converts the Non-Return to Zero (NRZ) data re-
ceived after separating the data from the QuASI inter-
face. The Manchester encoding process complements
the first half of the data bit. During the second half of
the data bit, the true value is sent. Manchester encod-
ing always guarantees a transition at the Bit Cell Center
(BCC). Transmission and encoding occur only when
the QTX_EN line is asserted during the appropriate
time slot.
Manchester Decoder
The QuEST device provides separate Manchester
decode circuits per receive channel. The Manchester
Decoder allows for extracting the clock and NRZ data
from the received Manchester data stream. After the
appropriate receive squelch paths have opened, the
Manchester decoder locks onto an incoming frame
within two bit times. The Manchester decoder incorpo-
rates a fast locking acquisition circuit during the begin-
ning of preamble. The Manchester decode circuit
discards approximately 3 bits of data during the data
acquisition phase. The maximum jitter tolerated is
13.5 ns on the 10BASE-T ports and 18 ns on the AUI
port. Manchester data which is decoded by the unit is
sent to the elasticity FIFO for rate decoupling.
Elasticity FIFO
The QuEST device incorporates a 10-bit elasticity
FIFO. The purpose of the elasticity FIFO is to rate
match the frequency of the incoming receive data to the
rate of the System Clock (SCLK).
Attachment Unit Interface (AUI)
General
The QuEST device provides an optional AUI that can
be allocated to port 0 of the four ports. The AUI allows
a non-10BASE-T MAU (i.e., 10BASE-2, 10BASE-5, or
10BASE-FL transceiver) to connect to port 0. When the
AUI interface is selected for port 0, the 10BASE-T cir-
cuit on that interface is disabled. If the 10BASE-T cir-
cuit is disabled, the 10BASE-T circuit will terminate the
transmission and reception of link pulses as well as
frame data. The AUI port will use the Manchester en-
coder/decoder circuitry of that port.
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