zl50012 Zarlink Semiconductor, zl50012 Datasheet - Page 27

• Manufacturer Part Number: zl50012
• Description: Flexible 512 Channel Tdm Digital Switch
• Manufacturer: Zarlink Semiconductor

2.5
The connection memory is 12-bit wide. There are 512 memory locations to support the ST-BUS serial outputs
STo0-15. The address of each connection memory location corresponds to an output destination stream number
and an output channel address. See Table 28 on page 52 for the connection memory address map.
When Bit 0 of the connection memory is low, Bit 1 to 7 define the source (input) channel address and Bit 8 to 11
define the source (input) stream address. Once the source stream and channel addresses are programmed by the
microprocessor, the contents of the data memory at the selected address are switched to the mapped output
stream and channel. See Table 29 on page 53 for details on the memory bit assignment when Bit 0 of the
connection memory is low.
When Bit 0 of the connection memory is high, Bit 1 and 2 define the per-channel control modes of the output
streams, the per-channel high impedance output control, the per-channel message and the per-channel BER test
modes. In the message mode, the 8-bit message data located in Bit 3 to 10 of the connection memory will be
transferred directly to the mapped output stream. See Table 30 on page 53 for details on the memory bit
assignment when Bit 0 of the connection memory is high.
2.5.1
This feature allows fast initialization of the entire connection memory after power up. When block programming
mode is enabled, the content of Bit 1 to 3 in the Internal Mode Selection (IMS) Register will be loaded into Bit 0 to 2
of all the 512 connection memory locations. The other bit positions of the connection memory will be loaded
with zeros.
Memory block programming procedure:
(Assumption: The MBPE and MBPS bits are both low at the start of the procedure)
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Note: Once the block programming is started, it can be terminated at any time prior to completion by setting the
MBPS bit or the MBPE bit to low. If the MBPE bit is used to terminate the block programming before completion,
users have to set the MBPS bit from high to low before enabling other device operation.
Program Bit 1 to 3 (BPD0 to BPD2) in the IMS (Internal Mode Selection) register.
Set the Memory Block Programming Enable (MBPE) bit in the Control Register to high to enable the block
programming mode.
Set the Memory Block Programming Start (MBPS) bit to high in the IMS Register to start the block
programming. The BPD0 to BPD2 bits will be loaded into Bit 0 to 2 of the connection memory. The other bit
positions of the connection memory will be loaded with zeros. The memory content after block programming
is shown in Table 8.
It takes 50µs for the connection memory to be loaded with the bit pattern defined by the BPD0 to BPD2 bits.
After loading the bit pattern to the entire connection memory, the device will reset the MBPS bit to low,
indicating that the process has finished.
Upon completion of the block programming, set the MBPE bit from high to low to disable the block
programming mode.
Connection Memory Block Programming
Connection Memory Description
11
0
10
0
Table 8 - Connection Memory in Block Programming Mode
9
0
8
0
7
0
Zarlink Semiconductor Inc.
ZL50012
6
0
30
5
0
4
0
3
0
BPD2
2
BPD1
1
BPD0
Data Sheet
0