zl30236 Zarlink Semiconductor, zl30236 Datasheet

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zl30236

Manufacturer Part Number
zl30236
Description
Dual Channel Universal Clock Generator
Manufacturer
Zarlink Semiconductor
Datasheet
Features
Operates from a single crystal resonator, clock
oscillator or voltage controlled oscillator
Two independently programmable clock
synthesizers generate any clock rate from 1 kHz to
720 MHz
Precision synthesizers generate clocks with jitter
below 0.7 ps RMS for 10 G PHYs
Supports programmable frequency offsets for clock
margining; or for use as a digitally controlled
oscillator
Eight LVPECL outputs; max rate 720 MHz
Four LVCMOS outputs; max rate 160 MHz
Dynamically Configurable via SPI/I2C interface
JTAG
Osco
Osci
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
ZL30236
Master
Clock
pwr_b
JTAG
Copyright 2010, Zarlink Semiconductor Inc. All Rights Reserved.
GPIO
Configuration
and Status
Figure 1 - Functional Block Diagram
SPI / I
Zarlink Semiconductor Inc.
2
C
Clock Generator 0 (Precision)
Clock Generator 1 (Precision)
Fs= Bs
Fs= Bs
Dual Channel Universal Clock Generator
Synthesizer 0
Synthesizer 1
0
1
*Ks
*Ks
1
0
1
*16*Ms
*16*Ms
Applications
ZL30236GGG
ZL30236GGG2
Timing for NPUs, FPGAs, Ethernet switches and
PCIe switches
Timing for 10 Gigabit CDRs, Rapid-IO, PCIe,
Serial MII, Star Fabric, Fibre Channel, XAUI
Processor clock, Processor bus clock, SDRAM
clock, DDR clock
0
1
/Ns
/Ns
0
1
Div A
Div B
Div C
Div D
Div A
Div B
Div C
Div D
*Pb Free Tin/Silver/Copper
Ordering Information
-40
100 Pin CABGA
100 Pin CABGA
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
Outputs
Outputs
o
C to +85
Short Form Data Sheet
o
C
hpdiff4_p/n
hpdiff5_p/n
hpoutclk2
hpoutclk3
hpdiff0_p/n
hpdiff1_p/n
hpdiff2_p/n
hpdiff3_p/n
hpoutclk0
hpoutclk1
hpdiff6_p/n
hpdiff7_p/n
*
ZL30236
Trays
Trays
April 2010

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zl30236 Summary of contents

Page 1

... Div C Div D Configuration and Status 2 SPI / I C Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. ZL30236 Short Form Data Sheet April 2010 Ordering Information 100 Pin CABGA Trays * 100 Pin CABGA Trays +85 C Outputs hpdiff0_p/n LVPECL hpdiff1_p/n ...

Page 2

... The free run synchronization solution allows designers to replace multiple, costly components with a highly integrated and programmable, single- chip solution. The ZL30236 device generates clocks from a single crystal, allowing designers to replace numerous oscillators traditionally used to provide timing for various components with one chip. ZL30236 2 Zarlink Semiconductor Inc ...

Page 3

... Mechanical Drawing ZL30236 3 Zarlink Semiconductor Inc. Short Form Data Sheet ...

Page 4

... Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are trademarks of Zarlink Semiconductor Inc. TECHNICAL DOCUMENTATION - NOT FOR RESALE ZL30236 visit our Web Site at www.zarlink.com C Patent rights to use these components ...

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