zl30121 Zarlink Semiconductor, zl30121 Datasheet - Page 14

• Manufacturer Part Number: zl30121
• Description: Sonet/sdh Low Jitter System Synchronizer
• Manufacturer: Zarlink Semiconductor

In addition to the reference inputs, DPLL1 has three optional frame pulse synchronization inputs (sync0 to sync2)
used to align the output frame pulses. The sync
or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of the
frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.
Each of the sync inputs accept a single-ended LVCMOS frame pulse. Since alignment is determined from the rising
edge of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width
requirement of 5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies
shown in Table 3.
Without a frame pulse
signal at the sync
input, the output
frame pulses will align
to any arbitrary cycle
of its associated
output clock.
When a frame pulse
signal is present at
the sync input, the
DPLL will align the
output frame pulses
to the output clock
edge that is aligned
to the input frame
pulse.
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies
diff
diff
x
x
/sdh_clk
/sdh_clk
Figure 4 - Output Frame Pulse Alignment
n = 0, 1, 2
x = 0, 1
n = 0, 1, 2
x = 0, 1
x
x
/p0_clk
/p0_clk
sdh_fp
sdh_fp
Zarlink Semiconductor Inc.
(48x 125 2s frames)
n
input is selected with its corresponding ref
x
x
/p1_clk
x
ZL30121
/p1_clk
x
/p0_fp
/p0_fp
166.67 Hz
sync
400 Hz
64 kHz
sync
1 kHz
2 kHz
8 kHz
ref
ref
14
n
n
x
x
x
n
x
n
- no frame pulse signal present
n
input, where n = 0, 1,
Data Sheet