mt8926ap Mitel, mt8926ap Datasheet - Page 16

• Manufacturer Part Number: mt8926ap
• Description: Iso-cmos T1 Performance Monitoring Adjunct Circuit Pmac
• Manufacturer: Mitel

MT8926
transition of the CRCR bit (CSTi1 channel 11 bit 5,
PMAC Control Word). This will ensure the CRC error
counter never overflows.
SLIP and SYN Interrupts
The MT8976 SLIP and SYN status bits are passed to
the PMAC via the MT8976/77 CSTo to PMAC CSTi0
connection. A MT8926 interrupt will be initiated when
the SLIP bit of the framer changes state. This is the
only interrupt source that does not have to be
cleared before another interrupt of that group can
make IRQ go low. Therefore, when IRQ is returned to
a high impedance condition after a SLIP interrupt
and all other G1 interrupts are quiescent, any G1
interrupt can make IRQ to go low.
‡ G2 interrupts are cleared when SEI, FSI, CSI and BSI = 0.
Note: AND denotes a logical and.
4-18
Signal
SEI
FSI
CSI
BSI
‡
SEI bit low to high AND other G2
interrupts quiescent AND IRQ
high impedance.
FSI bit low to high AND other G2
interrupts quiescent AND IRQ
high impedance.
CSI bit low to high AND other G2
interrupts quiescent AND IRQ
high impedance.
BSI bit low to high AND other G2
interrupts quiescent AND IRQ
high impedance.
To Trigger interrupt (IRQ low)
Table 17. Group Two (G2) Interrupt Activation and Clearing
The INTA bit of the PMAC Control Word (CSTi1 channel 11 bit
1) should be made low to clear the interrupt mechanism (IRQ
high impedance). All G2 interrupts must be clear and INTA
must be high before a further interrupt can be generated from
G2.
The SEI bit will remain clear as long as the INTA bit is low. SEI
can also be cleared (low) by toggling SER (CSTi1 channel 11 bit
7) from high to low.
FSI is cleared (low) by toggling FER (CSTi1 channel 11 bit 6)
from high to low.
CSI is cleared (low) by toggling CRCR (CSTi1 channel 11 bit 5)
from high to low. Valid for ESF only.
BSI is cleared (low) by toggling BPVR (CSTi1 channel 11 bit 4)
from high to low.
To Clear and Arm interrupt
A Low-to-High transition of the MT8976/77 SYN bit
will
synchronization situation may indicate that a loss of
signal condition (LOS) exists or that an all ones (AIS
or Blue Alarm) is being received. Therefore, the SYN
interrupt service routine should check the state of the
AIS and LOS bits of CSTo.
initiate
a
PMAC
(
IRQ high impedance)
interrupt.
This
loss
of