le79489 Zarlink Semiconductor, le79489 Datasheet - Page 9
![no-image](/images/manufacturer_photos/0/7/727/zarlink_semiconductor_sml.jpg)
le79489
Manufacturer Part Number
le79489
Description
Subscriber Line Interface Circuit
Manufacturer
Zarlink Semiconductor
Datasheet
1.LE79489.pdf
(18 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
le79489-2DJC
Manufacturer:
ZARLINK
Quantity:
2 583
Company:
Part Number:
le79489-2DJCT
Manufacturer:
ZARLINK
Quantity:
2 583
Company:
Part Number:
le79489-3DJC
Manufacturer:
ZARLINK
Quantity:
2 515
Company:
Part Number:
le79489-3DJCT
Manufacturer:
ZARLINK
Quantity:
2 515
Company:
Part Number:
le79489DJC
Manufacturer:
ZARLINK
Quantity:
6 934
Part Number:
le79489DJC
Manufacturer:
MICROSEMI/美高森美
Quantity:
20 000
RELAY DRIVER SCHEMATICS
Notes:
1. Unless otherwise specified, test conditions are V
2. a. Overload level exists when THD = 1%.
3. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
6. Group delay can be greatly reduced by using a Z
7. Minimum current level is guaranteed not to cause a false Loop Detect. The SLIC must be functional in this condition.
8. Four-wire performance is 5–9 dB better than the specified two-wire values.
9. Open loop, Active state, Metering mode power dissipation may be reduced from a typical of 550 mW to a typical of 150 mW by connecting
Ω, R
= 1, two-wire AC input impedance is a 600 Ω resistance synthesized by the programming network shown below.
b. Overload level exists when THD = 1.5%.
less than 2 µs and increases 2WRL. The effect of group delay on linecard performance also may be compensated for by synthesizing
complex impedance with the DSLAC™ or QSLAC™ device.
the DET pin to the OVH pin. This connection will force the SLIC into the nonmetering mode while on hook. With this connection, a me-
tering signal sent after the SLIC goes on hook may be distorted on the 2W line because the SLIC is forced into the nonmetering mode. To
eliminate this distortion, a delay can be added between the time the SLIC goes on hook and the time the SLIC switches to nonmetering
mode by using an RC circuit for the DET pin to OVH pin connection.
D
= 35.4 kΩ, RFA = 0 Ω, no fuse resistors, C
BGND
VTX
RSN
R
R
T1
T2
= 76 kΩ
= 76 kΩ
RINGOUT
CC
HP
T
= +5 V, BAT1 = –50 V, BAT2 = –34 V, R
R
= 0.22 µF, C
network such as that shown in Note 1 above. The network reduces the group delay to
RX
Zarlink Semiconductor Inc.
= 150 kΩ
DC
9
= 0.5 µF, C
C
CAS
T1
= 120 pF
= 0.33 µF, C
BGND
L
V
= 600 Ω, R
RX
VBAT12
DC1
= 220 nF, D
= R
DC2
= 5.833 kΩ, R
1
= D
TESTOUT
2
= 1N400x, OVH
TMG
= 570