le5711 Zarlink Semiconductor, le5711 Datasheet
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le5711
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le5711 Summary of contents
Page 1
... POTS applications requiring a small footprint SLIC device with significant power savings. By combining the line interface of two channels into one SLIC device, the Le5711 device enables the design of a low cost, high performance, and fully programmable line interface for multiple country applications worldwide ...
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... Ring-Trip Detector Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Loop Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 SLIC Device Decoding User-Programmable Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Application Circuit .15 Line card Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Physical Dimensions .17 32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Revision .19 Revision .19 Revision .19 Revision .19 2 Zarlink Semiconductor Inc. ...
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... The Le5711 device is designed for long loop high-density POTS applications requiring a low power, small footprint SLIC. The Le5711 device increases linecard density by integrating two SLIC devices into a single 32 pin package. This reduction in board space allows for higher density linecard, which allows for amortizing common hardware across more channels. The Le5711 device gives linecard designers a simple control interface that supports four states: Active, Reverse Polarity, Standby, and Disconnect (Ringing) ...
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... Exposed Pad Zarlink Semiconductor Inc. BGND (RING (TIP DAC 25 VBAT ...
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... Transmit audio signal of channel 2. This output is a scaled version of the A and B metallic voltage. VTX also sources the two-wire input impedance programming network. 2 The exposed thermal management pad must be in thermal contact with an exposed copper plate with an electrical potential of battery supply (VBAT pin). 5 Zarlink Semiconductor Inc (RING (RING). ...
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... The thermal performance of a thermally enhanced package is assured through optimized printed circuit board layout. Refer to the Thermal Management for the Le5711 and Le5712 Dual SLIC Devices Application Note for details. Package Assembly The green package devices are assembled with enhanced, environmental compatible lead-free, halogen-free, and antimony-free materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead- free board assembly processes. The peak soldering temperature should not exceed 245° ...
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... On hook –0.35 300 to 3.4 kHz –0.15 relative to 1 kHz +3 dBm to –55 dBm –0.15 relative to 0 dBm 0 dBm to –37 dBm –0.15 +3 dBm to 0 dBm –0.35 7 Zarlink Semiconductor Inc. Min Typ Max Unit 26 dB Ω –50 +50 mV 2.5 Vpk 1.1 –64 – ...
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... Both channels, Active state, BAT = –48 V Test Conditions Min f = .01 to 100 MHz HF gen output = 1.5 Vrms AXi BXi 2.2 nF AXi BXi Test Conditions Min –75 –400 8 Zarlink Semiconductor Inc. Typ Max Unit 100 µA +40.3 V Typ Max Unit ...
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... On-hook threshold Standby Hysteresis Notes: 1. Unless otherwise noted, the test conditions are set up by the Le5711 device test circuit as illustrated Overload level is defined as THD = 1%. b. Overload level is defined when THD = 1.5%. 3. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests. ...
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... 0. Zarlink Semiconductor Inc. Description connected between the VTX and RSN pins. The Ti fuse resistors are R , and Z is the desired 2-wire AC F 2WIN input impedance. When computing Z , the internal Ti current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account ...
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... -------------- where R AB1 REF 303 Ω 43 – AB2a 3 – AB2b AB2a 111 Ω – 1 – AB3a BAT L ⋅ – 0.33 V AB3b AB3a BAT 11 Zarlink Semiconductor Inc REF ' = 10.8 ...
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... VTX 2 SLIC V AB AGND RSN (RING RSN log L2 VTX (TIP VTX 2 SLIC AGND RSN (RING RSN log L4 BRS = 20 log Zarlink Semiconductor Inc. R REF ...
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... SLIC AGND = 600 Ω RSN (RING) RSN Figure 6. RFI Test Circuit C 1 200Ω 50Ω RF 200Ω RF 50Ω Zarlink Semiconductor Inc 120 124 K RX ...
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... Figure 7. Le5711 Test Circuit BGND 2.2 nF TIP A (TIP HP1 100 nF RING B (RING BX1 2 TMG1 TMG 1600 Ω VBH BAT VBAT 1600 Ω TMG 2 R TMG2 DAC DAC C AX2 2.2 nF TIP A (TIP ...
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... 400 Ω R SR1 1.82 MΩ RT2 SR2 RT1 MΩ BGND VCC RSVD 1 Le5711 C AX1 (TIP HP1 100 nF CH1 R HP1 15 kΩ B (RING BX1 R TMG1 TMG 1 2.49 kΩ VBAT R TMG2 ...
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... TH2 R * DAC Note Shared between four DualSLIC device packages 2. Refer to the Thermal Management for the Le5711 and Le5712 Dual Devices Application Note for particular conditions. Type Value Capacitor (X7R Capacitor (X7R) 100 nF Capacitor (X7R) 100 nF Capacitor (X7R Capacitor (X7R) 1.5 µ ...
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... Exact shape of this feature is optional. 0.550 0.553 5 Details of pin 1 identifier are optional but must be located -- 10 deg within the zone indicated. 6 Sum of DAM bar protrusions to be 0.007 max per lead. 7 Controlling dimension : Inch. 8 Reference document : JEDEC MS-016 32-Pin PLCC 17 Zarlink Semiconductor Inc. ...
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... Markings will vary with the mold tool used in manufacturing. Min Nom Max Symbol Min - - 1.20 c 0.09 0.05 - 0.15 L 0.45 0.95 1.00 1. BSC S 0.20 10 BSC b 0.17 12 BSC e 10 BSC D2 0.08 - 0. aaa 0 deg 3.5 deg 7 deg bbb 0 deg - - ccc 11 deg 12 deg 13 deg ddd 11 deg 12 deg 13 deg N 44-Pin eTQFP 18 Zarlink Semiconductor Inc. Nom Max - 0.20 0.60 0.75 1.00 REF - - 0.20 0.27 0.80 BSC 8.00 8.00 0.20 0.20 0.10 0.20 44 ...
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... Removed non-green OPNs from • Removed Le57D113JC and Le57D113DJC from Revision • Removed Le57D113BTC from Ordering Information, on page Revision • Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007 Ordering Information, on page 1. Ordering Information, on page 1. 19 Zarlink Semiconductor Inc. 1. ...
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... For more information about all Zarlink products Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use ...