mt8885an1 Zarlink Semiconductor, mt8885an1 Datasheet - Page 14

• Manufacturer Part Number: mt8885an1
• Description: Integrated Dtmf Transceiver With Power-down And Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor

Bit
b0
b1
b2
b3
MC68HC11
AD0-AD3
A8-A15
CP/DTMF
Figure 12 a) & b) - MT8885 Interface Connections for Various Intel and Motorola Micros
RW
Name
TOUT
RSEL
AS
IRQ
E
12 (a) Motorola
Tone Output Control. A logic high enables the tone output; a logic low puts the DTMF
transmitter in power-down mode. The TONE output pin is held in high impedance and the
transmit register is cleared. See Note 1 below.
Call Progress or DTMF Mode Select. A logic high enables the receive call progress mode;
a logic low enables DTMF mode. In DTMF mode the device is capable of receiving and
transmitting DTMF signals. In CP mode a rectangular wave representation of the received
tone signal will be present on the IRQ/CP output pin if IRQ has been enabled (control
register A, b2=1). In order to be detected, CP signals must be within the bandwidth
specified in the AC Electrical Characteristics for Call Progress.
Note: DTMF signals cannot be detected when CP mode is selected.
Interrupt Enable. A logic high enables the interrupt function; a logic low de-activates the
interrupt function. When IRQ is enabled and DTMF mode is selected (control register A,
b1=0), the IRQ/CP output pin will go low when either 1) a valid DTMF signal has been
received for a valid guard time duration, or 2) the transmitter is ready for more data (burst
mode only).
Register Select. A logic high selects control register B for the next write cycle to the control
register address. After writing to control register B, the following control register write cycle
will be directed to control register A.
Table 6 - Control Register A Description
CS
D0-D3
RS0
DS/RD
R/W/WR
MT8885
Zarlink Semiconductor Inc.
MT8885
14
Description
8031/8051/
8080/8085
A8-A15
ALE
WR
RD
P0
12 (b) Intel
CS
D0-D3
RS0
DS/RD
R/W/WR
MT8885
Data Sheet