mt8889csr1 Zarlink Semiconductor, mt8889csr1 Datasheet - Page 15

• Manufacturer Part Number: mt8889csr1
• Description: Integrated Dtmf Transceiver With Adaptive Micro Interface
• Manufacturer: Zarlink Semiconductor

BIT
BIT
b0
b1
b2
b3
b0
b1
b2
b3
TRANSMIT DATA
REGISTER EMPTY
(BURST MODE ONLY)
RECEIVE DATA REGISTER
FULL
DELAYED STEERING
BURST
NAME
TEST
S/D
C/R
NAME
IRQ
Burst Mode Select. A logic high de-activates burst mode; a logic low enables burst mode. When
activated, the digital code representing a DTMF signal (see Table 1) can be written to the transmit
register, which will result in a transmit DTMF tone burst and pause of equal durations (typically 51
msec). Following the pause, the status register will be updated (b1 - Transmit Data Register Empty),
and an interrupt will occur if the interrupt mode has been enabled.
When CP mode (control register A, b1) is enabled the normal tone burst and pause durations are
extended from a typical duration of 51 msec to 102 msec.
When BURST is high (de-activated) the transmit tone burst duration is determined by the TOUT bit
(control register A, b0).
Test Mode Control. A logic high enables the test mode; a logic low de-activates the test mode.
When TEST is enabled and DTMF mode is selected (control register A, b1=0), the signal present on
the IRQ/CP pin will be analogous to the state of the DELAYED STEERING bit of the status register
(see Figure 7, signal b3).
Single or Dual Tone Generation. A logic high selects the single tone output; a logic low selects the
dual tone (DTMF) output. The single tone generation function requires further selection of either the
row or column tones (low or high group) through the C/R bit (control register B, b3).
Column or Row Tone Select. A logic high selects a column tone output; a logic low selects a row
tone output. This function is used in conjunction with the S/D bit (control register B, b2).
Table 7 - Control Register B Description
Table 8 - Status Register Description
Interrupt has occurred. Bit one (b1)
or bit two (b2) is set.
transmitter is ready for new data.
Valid data is in the Receive Data
Register.
Set upon the valid detection of the
absence of a DTMF signal.
Pause duration has terminated and
Zarlink Semiconductor Inc.
STATUS FLAG SET
MT8889C
15
DESCRIPTION
Interrupt is inactive. Cleared after
Status Register is read.
Cleared after Status Register is read
or when in non-burst mode.
Cleared after Status Register is read.
Cleared upon the detection of a valid
DTMF signal.
STATUS FLAG CLEARED
Data Sheet