ml86v7668a Oki Semiconductor, ml86v7668a Datasheet
ml86v7668a
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ml86v7668a Summary of contents
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... The ML86V7668A is fully pin-compatible with the ML86V7668. USES AND APPLICATIONS The ML86V7668A that can be used as an interface for video signal input of any digital video processing system. The device can be operated with a digital PLL line lock clock for applications where image quality is of utmost importance ...
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... Polarity inversion of the field signal and vertical sync signal Other Sections 2 I C-bus interface I/O: 3.3 V power supply, Core: 2.5 V power supply Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) FEDL86V7668A-01 ML86V7668A 2 C-bus : ITU-R BT.656 mode : 8-bit mode : 16-bit mode : 18-bit RGB mode 2/32 ...
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... OKI Semiconductor BLOCK DIAGRAM Decimation Filter Decimation Filter 10bit ADC 10bit ADC (ch1) (ch2) LPF LPF AMP / AMP / Analog AGC Analog AGC Clamp Composite / Y Chrominance Input SEL Input SEL FEDL86V7668A-01 ML86V7668A 3/32 ...
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... LPF 89 PLL VREF 90 PVDD 91 TEST[6] 92 TEST[5] 93 TEST[4] 94 TEST[3] 95 TEST[2] 96 DIGITAL TEST[1] 97 TEST[0] 98 DVDDIO 99 DGNDIO 100 100-Pin Plastic TQFP (TQFP100-P-1414-0.50-K) DIGITAL DIGITAL ANALOG FEDL86V7668A-01 ML86V7668A 50 DVDDIO 49 VSYNC_L 48 HSYNC_L 47 DGNDCO 46 CLKX2 45 DVDDCO 44 PLLSEL 43 INSSEL 42 GAINS[0] 41 GAINS[1] 40 GAINS[2] 39 GAINS[3] INS[0] 38 INS[1] 37 INS[ ...
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... Digital core ground Reset signal input ¾ Digital IO power supply (3.3 V) ¾ Digital IO ground ¾ Digital core power supply (2.5 V) External clock input ¾ Digital core ground Horizontal sync signal output Vertical sync signal output ¾ Digital IO power supply (3.3 V) FEDL86V7668A-01 ML86V7668A Function 5/32 ...
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... PLL is used; connect to PVDD when PLL not used) Center frequency select (Leave open when PLL is used; connect to PVDD when PLL not used) ¾ PLL power supply (3.3 V) Test pins (Normally leave open) ¾ Digital IO power supply (3.3 V) ¾ Digital IO ground FEDL86V7668A-01 ML86V7668A Function 6/32 ...
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... VIN1 VIN2 VIN3 VIN4 Pin 8 Pin 10 Pin 11 Pin 12 Composite Composite Composite Composite Luminance Luminance Luminance OFF (ADC sleep) FEDL86V7668A-01 ML86V7668A ADC operation setting VIN5 VIN6 VIN7 Pin 14 Pin 15 Pin 16 ADC1: ON ADC2: OFF ADC1: ON ADC2: OFF ADC1: ON ADC2: OFF ADC1: ON ADC2: OFF ...
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... Register Gain factor $69/ADC2[5:0] 11_1111 1.014 11_0001 1.263 10_0110 1.565 01_1101 1.946 01_0110 2.400 01_0000 3.000 00_1011 3.789 00_0111 4.800 00_0100 6.000 (00_0010) (00_0000) (Setting prohibited) -- FEDL86V7668A-01 ML86V7668A 8/32 ...
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... Trap filter 011 3-line comb or trap adaptive filter 100 Undefined 101 2-line or 3-line adaptive transition filter 110 Undefined 111 Undefined FEDL86V7668A-01 ML86V7668A PAL Y/C separation Adaptive filter 2-line comb filter Trap filter Undefined Undefined Undefined Undefined 2-line comb or trap adaptive transition filter 9/32 ...
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... Aperture bandpass filter and coring filter that are used for contour compensation These filters are adjusted using the following registers: - For setting the aperture band-pass filter coefficient: # Related register: $35/LUMC4[6:5] - For setting the range of coring # Related registers: $35/LUMC4[4:3] - For setting aperture weight # Related register: $35/LUMC4[2:0] FEDL86V7668A-01 ML86V7668A 10/32 ...
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... ITU-R BT.656 Y/CbCr 8 bits Y/CbCr 16 bits Y/CbCr 16 bits RGB 18 bits *: Default Output Formats Register IOC2[0] = “0” * IOC2[0] = “1” Control pin (Pins 30, 31) MODE[3:2] (i) 4:2:2 [00] (i) 4:2:2 [01] (i) 4:2:2 [10] (i) 4:1:1 [10] (i) 4:4:4 [11] FEDL86V7668A-01 ML86V7668A Register Register Register IOC2[5:4] IOC2[1] [00 [01] 0 [10] 0 [10] 1 [11] 0 11/32 ...
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... Input clock operating mode. (See the table below) $70/PLLC1[6] = “1” 25 MHz $01/IOC2[0] = “1” Register $00/IOC1[ FEDL86V7668A-01 ML86V7668A Sampling Asynchronous $70/PLLC1[7] = “0” * Line lock $70/PLLC1[7] = “1” Fixed PLL clock Sampling clock (double-speed) Pin 46 CLKX2 27 MHz 24.545454 MHz 12/32 ...
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... Detects color stripes, false pulses, and MV protection and sets flags. MV protection: Outdated copy protedction signal that was being used in VTRs specicial signal whose vertical-serration-pulse width is 10 ms. # Related registers: $81/VBIDM, $89/RSTVBID, $90/STATUS1, $91/STATUS2, $92/VFLAG Note: This function does not detect SECAM color stripes. FEDL86V7668A-01 ML86V7668A 13/32 ...
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... This serial interface block is based on the I 89h are write/read, while the registers at 90h and onwards are read-only. Test Control Block This block is used to test the LSI chip not intended for user use standard of Phillips Corporation. The registers subaddress FEDL86V7668A-01 ML86V7668A 14/32 ...
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... Ta = 25° 25°C Ios — — Condition Min. — 3.0 — 2.25 — 3.0 — 3.0 — 3.0 — — — 0.8 VDD1 — –0.3 — –40 FEDL86V7668A-01 ML86V7668A Rating Unit –0.3 to +4.6 V –0.3 to +3.6 V –0.3 to +3.9 V 800 –55 to +150 °C Typ. Max. Unit 3.3 3.6 V 2.5 2.75 V 3.3 3 ...
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... POWER-ON SEQUENCE Follow the sequence shown below when turning the power on. At power ON DVDDIO AVDD ADVDD PVDD DVDDCO 0 ms min min min min. FEDL86V7668A-01 ML86V7668A At power shut-down min min. ...
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... SLEEP = “1” IDDS INS[2:0] = “111” Condition Min. ITU-R BT.601 — NTSC Square — 24.545454 Pixel — 45 — — — — — — — 200 FEDL86V7668A-01 ML86V7668A Min. Typ. Max. Unit — — V — — 0 –10 — +10 mA –10 — + — ...
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... Register IOC3[ (default) Register IOC3[ Y[7:0] C[7:0] VSYNC_L HSYNC_L STATUS[6:1] Reset Timing VDD POWER OFF ON See clock oscillator’s data sheet GND CLKX2 RESET_L Note: Output data goes to H-Z at reset. tclkx2 tcdx2o tcdxo todx2 Setup Time Valid Clock rst_w Don’t Care FEDL86V7668A-01 ML86V7668A 18/32 ...
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... I C Specifications (Fast Mode) Min. 0 4.7 4.0 4.7 4.0 4.7 0 (300) 250 4.0 C Specifications (High Speed Mode) Min. 0 1.3 0.6 1.3 0.6 0.6 0 (300) 100 0.6 FEDL86V7668A-01 ML86V7668A tHD:STA P tSU:STO Typ. Max. Unit 100 kHz 300 ns ms Typ. Max. Unit 400 kHz ...
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... Vertical Sync Signals (NTSC Vertical Sync Signals (PAL) FEDL86V7668A-01 ML86V7668A 283 284 285 20/32 ...
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... The delay value becomes approx. 2.5H only when the adaptive filter (register $10/YC1[6:4] = “000”) is selected as the Y/C separation filter in PAL mode. Data delay Blank HSYNC delay Input signal Mode Composite FIFO-1, 2 Composite FIFO through Composite FIFO-1, 2 Composite FIFO through FEDL86V7668A-01 ML86V7668A Active Data Delay Approx. 1.5H Approx. 1.5H Approx. 1.5H Approx. 1.5H 21/32 ...
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... FEDL86V7668A-01 ML86V7668A 60 pixels Total line Active line (VVALID = H) V Active V blank Total line line Odd/20 Odd/243 Odd/262.5 Even/20 Even/242 Even/262.5 Odd/24 Odd/288 Odd/312.5 Even/25 Even/288 Even/312 ...
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... Each VALID signal and the ODD/EVEN signal are selected by the STATUS signal. VSYNC_L, ODD/EVEN HSYNC_L VSYNC_L 1 pixel ODD/EVEN (STATUS4) ODD/EVEN (STATUS4) VALID Signal HSYNC_L 60 pixels Front porch Back porch HVALID (STATUS5) 2 pixels VVALID (STATUS6) 60 pixels 1/2 H ODD 1 pixel EVEN FEDL86V7668A-01 ML86V7668A 0 pixel 23/32 ...
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... Y/CbCr (8 bits ( bits (CbCr) (4:1:1)) (CLKX2O and CLKXO output setting ($02/IOC3 [1:0]): default) CLKX2O CLKXO HVALID Y[7:0] Y-1 Y0 C[7:0] Cr-2 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Crm Cr0 Cb2 Cr2 Cr0 “00” “00” FEDL86V7668A-01 ML86V7668A Yn-2 Cbm Yn-1 Crm Yn Cbm+1 Yn-1 Yn Cbm Crm Yn-1 Yn Yn+1 “00” “00” Cbm+1 24/32 ...
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... G [5:0] G [5:0] B [5:0] R-1 R0 18-bit RGB (6 bits ( bits ( bits (B)) QVGA output (CLKX2O, CLKXO, and QVGA output clock setting ($02/IOC3 [2:0]): default) CLKX2O CLKXO QVGA CLK (STATUS4) HVALID G [5:0] G [5:0] B [5:0] R FEDL86V7668A-01 ML86V7668A Gn-1 Gn Bn Gn+1 Bn Bn+1 Rn Rn+1 25/32 ...
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... Video data block 1440T (PAL/NTSC) Multiplexed video data Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 ------- Cr718 Y719 4T Digital line Total pixels Active pixels SAV: Start of active video timing reference code EAV: End of active video timing reference code T: Clock period 37ns (1/27MHz) FEDL86V7668A-01 ML86V7668A 120T 26/32 ...
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... FEDL86V7668A-01 ML86V7668A HEX LSB [2] [1] [ ...
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... FEDL86V7668A-01 ML86V7668A HEX LSB [2] [1] [ ...
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... Before using the decoder, please carefully evaluate and consider the signal conditions and usage environment of the intended use. In addition to this Data Sheet, an ML86V7668A User's Manual is also available. The User's Manual explains each register and provides examples of adapted circuits as well as other information helpful in the design phase. Please read the User's Manual before embarking on design work ...
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... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). FEDL86V7668A-01 ML86V7668A (Unit: mm) 30/32 ...
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... OKI Semiconductor REVISION HISTORY Document No. Date FEDL86V7668A-01 Jan. 29, 2007 Page Previous Current Edition Edition – – Final edition 1 FEDL86V7668A-01 ML86V7668A Description 31/32 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. FEDL86V7668A-01 ML86V7668A Copyright 2007 Oki Electric Industry Co., Ltd. 32/32 ...