ml86v7655 Oki Semiconductor, ml86v7655 Datasheet
ml86v7655
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ml86v7655 Summary of contents
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... NTSC/PAL-Compatible, 6ch DAC-Equipped Digital Video Encoder with Format Conversion Function GENERAL DESCRIPTION The ML86V7655 is an NTSC/PAL compatible digital video encode. It encodes digital image data such as ITU-R BT.656 and ITU-R BT.601 to analog video signals. As digital input, RGB (4:4:4), YCbCr (4:4:4), and progressive scan signals are supported besides generic ITU-R BT ...
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... Supports Macrovision copyguard function (only available in the ML86V7656) Conforms to version 7.1.L1 for interlace Conforms to version 1.2 for progressive • I2C-bus type serial interface • Supply voltage: 3.3 V (I/O supply)/2.5 V (core supply) (SCL and SDA pins only tolerant) • Package: 100-pin plastic TQFP (TQFP100-P-1414-0.5-K) (ML86V7655TB/ML86V7656TB) PEDL7655/56-000 ML86V7655/56 2/22 ...
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Progressive YD 9:0 to Input Data CD 9:0 Interlace Decoder BD 9:0 Interlace to Progressive IMOD 2:0 TEST 5:0 IRGB FOUT IPAL OCSYNC/OHSYNC IPRG I2C Interface OVSYNC Sync generator I444 OCLKX1 Timing controller ORGB VSYNC_L OPRG HSYNC_L CLKX2 CSYNC_L RESET_L ...
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... IMOD2 11 IPAL 12 IRGB 13 IPRG 14 I444 15 16 ORGB OPRG 17 RESET_L 18 TEST0 19 TEST1 20 TEST2 21 TEST3 22 23 TEST4 24 CLKX2 DGND2 25 100-Pin Plastic TQFP PEDL7655/56-000 ML86V7655/56 75 DGND1 74 STANDBY OLC 73 OLR 72 OLG 71 70 OLB 69 OCSYNC / OHSYNC 68 OVSYNC 67 DGND2 66 DVDD2 65 BD0 64 BD1 63 BD2 62 BD3 61 BD4 60 BD5 ...
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... When in master mode: output; when in slave mode: input BLANK signal input-output pin When in master mode: output; when in slave mode: input Video signal input pin; Brightness Y, G signal, bit[9] Video signal input pin; Brightness Y, G signal, bit[8] Video signal input pin; Brightness Y, G signal, bit[7] PEDL7655/56-000 ML86V7655/56 5/22 ...
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... Overlay text color (green) input pin Overlay text color (red) input pin Transparency control. When set to “1”, an overlay signal is displayed. Connect this pin to GND not used. Standby enable input pin “1”: Standby, “0”: Normal operation PEDL7655/56-000 ML86V7655/56 6/22 ...
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... Reference voltage input pin Video output full-scale adjustment pin Internal reference voltage output pin Analog power supply Composite signal output pin Analog GND Separate C signal output pin Analog power supply No connection Separate Y signal output pin Analog GND No connection No connection I/O GND PEDL7655/56-000 ML86V7655/56 7/22 ...
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... Min. Typ. VDD1 3.0 3.3 VDD2 2.25 2.5 AVDD 3.0 3.3 T –40 — — 1.23 refex R 500 1000 iadj R — 300 L PEDL7655/56-000 ML86V7655/56 Rating Unit –0 +4 –0 +3 –0 +4 –0 +6 –55 to +150 C Max. Unit 3.6 V 2.75 V 3.6 V +85 C — ...
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... OUT CLKX2 = 36 MHz, I DD1 R = 300 L CLKX2 = 0 MHz DDS1 IN IL CLKX2 = 0 MHz DDS2 STANDBY = V IH Condition — REFIN — — PEDL7655/56-000 ML86V7655/56 DGND1, DGND2, AGND = 0 V Min. Typ. Max. Unit VDD1 2.2 — V +0.3V 2.2 — 5.5 V –0.3 — +0.8 V — — 2.1 V 0.7 — ...
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... — L — 100 Rpull_up = 4 Rpull_up = 4 Rpull_up = 4.7 k 4.7 Rpull_up = 4.7 k 250 Rpull_up = 4 PEDL7655/56-000 ML86V7655/56 DGND1, DGND2, AGND = 0 V Typ. Max. Unit 24.545454 — MHz 29.5 — MHz 28.636364 — MHz 27 — MHz 36 — MHz — — ...
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... After every power supply reaches its specified voltage and the clock CLKX2 is stabilized, input the reset signal. RESET INPUT TIMING Input the reset signal for the reset pulse time t RESET_L Figure 1 Reset Signal Input Timing AVDD DVDD2. Turn them off in the reverse . RSTP tRSTP PEDL7655/56-000 ML86V7655/56 11/22 ...
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... Restart condition Slave address “100_010X” Specify X from the SLA pin (“1” or “0”) Write Read Acknowledge (slave) Acknowledge (master) Subaddress Write and read data at subaddress Stop condition PEDL7655/56-000 ML86V7655/ Stop Condition Data Data Am ……….. Am ...
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... YD, CD, BD OLC, OLR, OLG, OLB (2) Output timing CLKX2 Output signal Output signal: VSYNC_L, HSYNC_L, BLANK_L, OVSYNC, OCSYNC/OHSYNC, FOUT, OCLKX1 (VSYNC_L, HSYNC_L, and BLANK_L are configured as output pins in master mode PEDL7655/56-000 ML86V7655/56 VIH VIL VIH VIL VIH VIL VIH VIL 13/22 ...
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... This block adds a synchronization signal to the video signal, adds VBI data, and adjusts the synchronization signal level and offset of the signal. (9) CGMS/WSS/CC Controller This block generates data of CGMS-A(Copy Generation Management System - Analog), WSS (Wide Screen Signaling), and CC (Closed Caption). (10) LPF Removes high frequency components from video data. PEDL7655/56-000 ML86V7655/56 14/22 ...
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... In the slave mode, operation is based on synchronization signals input from outside. In the master mode, operation is based on synchronization signals generated within the LSI. (14) I2C Interface 2 I C-bus serial interface. Used to set operation modes and internal register values. PEDL7655/56-000 ML86V7655/56 load. 15/22 ...
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... OKI Semiconductor VIDEO DATA INPUT CONTROL (1) Types of input video pixel frequencies The ML86V7655/56 support the pixel frequencies for input video shown in Table 2. Every pixel frequency can be selected. (Note) The input clock frequency should be double the pixel frequency. Table 2 Types of Input Pixel Frequencies ...
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... OKI Semiconductor (3) Video data/synchronization information multiplexing input format types The ML86V7655/56 support the video data/synchronization information multiplexing input interfaces and data multiplexing (no multiplexing for sync signals) input interfaces shown in Table 5. Table 5 Types of Multiplexed Input Interfaces Input interface NTSC ITU-R BT656 style(*1) ...
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... Table 7 shows the output pins from which video data is output. Change the internal register values to enable/disable D/A converter output for each channel. Output format interlaced/progressive Output format YCbCr S-Video interlaced Table 7 Vidieo Output Pins Pin name Composite CVBS S-Video YS, CS YCbCr/RGB Y/G, Cb/B, Cr/R PEDL7655/56-000 ML86V7655/56 YCbCr RGB RGB progressive interlaced progressive 18/22 ...
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... GGAIN[7:0] BGAIN[7:0] RGAIN[7:0] DACOFF[5:0] Reserved Reserved Reserved - - - - - - - Reserved CCLN [4:0] CCOD0 [7:0] CCOD1 [7:0] CCED0 [7:0] CCED1 [7:0] Reserved WD01 [5:0] WD02 [7:0] CRCDATA[5:0] GP12 [7:0] GP34 [5:0] Reserved PEDL7655/56-000 ML86V7655/56 Bit 2 Bit 1 Bit 0 IMODSEL[2:0] I444SEL IRGBSEL IPRGSEL CSSEL ORGBSEL OPRGSEL SETUP OUTLEV[1:0] Reserved DMASK2 BLKADJ[3:0] SYNCLEV2(COMP)[2:0] LUMLEV[3:0] CCSTAT [1:0] 19/22 ...
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... Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). PEDL7655/56-000 ML86V7655/56 (Unit: mm) Package material Epoxy resin Lead frame material ...
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... OKI Semiconductor REVISION HISTORY Document Date No. PEDL7655-000 Sep. 14, 2004 Page Previous Current Edition Edition – – Preliminary edition 1 PEDL7655/56-000 ML86V7655/56 Description 21/22 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. PEDL7655/56-000 ML86V7655/56 Copyright 2004 Oki Electric Industry Co., Ltd. 22/22 ...