ml86v7668 Oki Semiconductor, ml86v7668 Datasheet
ml86v7668
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ml86v7668 Summary of contents
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... USES AND APPLICATION EXAMPLES The ML86V7668 that can be used as an interface for video signal input of any digital video processing system. The device can be operated with a digital PLL line lock clock for applications where image quality is of utmost importance ...
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... Screen scaling feature (QVGA) Gamma correction function (only RGB output mode) Sleep mode Output pin Hi-Z mode Other Sections 2 I C-bus interface I/O: 3.3 V power supply, Core: 2.5 V power supply Package: 100-pin plastic TQFP (TQFP100-P-1414-0.50-K) PEDL86V7668-01 ML86V7668 2 C-bus 2/31 ...
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... CLKXO CLKX2O CLKX2 PLLSEL VREF LPF Decimation Filter MODE[3:0] Decimation Filter 10-bit A/D C 10-bit A/D C (ch1) (ch2) LPF LPF AMP / AMP / Analog AGC Analog AGC Clamp Composite / Y Chrominance Input SEL Input SEL PEDL86V7668-01 ML86V7668 RESET_L SDA SCL SAS TEST[6:0] SCAN INSSEL GAINS[3:0] INS[2:0] 3/31 ...
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... LPF 89 PLL VREF 90 PVDD 91 TEST[6] 92 TEST[5] 93 TEST[4] 94 TEST[3] 95 TEST[2] 96 DIGITAL TEST[1] 97 TEST[0] 98 DVDDIO 99 DGNDIO 100 100-Pin Plastic TQFP (TQFP100-P-1414-0.50-K) DIGITAL DIGITAL ANALOG PEDL86V7668-01 ML86V7668 50 DVDDIO 49 VSYNC_L 48 HSYNC_L 47 DGNDCO 46 CLKX2 45 DVDDCO 44 PLLSEL 43 INSSEL 42 GAINS[0] 41 GAINS[1] 40 GAINS[2] 39 GAINS[3] INS[0] 38 INS[1] 37 INS[ ...
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... Digital core power supply Digital core ground Sleep signal input. “ 0” : Normal operation, “ 1” : Sleep operation I Reset signal input. “ 0” : Reset, 1: Normal operation I Reset after power is turned on. PEDL86V7668-01 ML86V7668 Open Open Open Open Open Open 5/31 ...
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... Amplifier gain setting: Pins GAINS[3:0] are used Input pin setting: Pins INS[2:0]) are used I 1: Register mode Amplifier gain setting: Register $69/ADC2[5:0] Input pin setting: Register $68/ADC1[2:0] The internal register setting is invalid when the external pin mode is set. PEDL86V7668-01 ML86V7668 6/31 ...
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... Digital core ground Data output Y[7]:MSB - Y[0] ITU-R BT.656 mode : YCbCr 8-bit data output 8-bit Y/CbCr mode : YCbCr 8-bit data output O 16-bit Y/CbCr mode : 8-bit(Y) data output 18-bit RGB mode : Y[7:4]=B[3:0] : Y[3:0]=G[5:2] The output mode is set by pins 30 and 31, or register $01/IOC2[5:4]. PEDL86V7668-01 ML86V7668 7/31 ...
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... Refer to the sample circuits provided in the User's Manual. PLL center frequency setting pin. Connect this pin to the "1" state O when not used. PLL power supply I Not used. Fixed to "0". Digital IO power supply Digital IO ground PEDL86V7668-01 ML86V7668 8/31 ...
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... Y/C Separation Function With the Y/C separation filter, composite data is separated into Y (luminance) data and C (chrominance) data. There are various Y/C separation filters available, which can be selected in an internal register. Y/C separation of the SECAM signal is performed by the trap filter. # Related register: $10/YC1, $11/YC2 PEDL86V7668-01 ML86V7668 9/31 ...
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... ACC correction circuit to maintain a stable chroma level, before performing UV decoding. The result of the UV decoding is passed through a low-pass filter and output as a chrominance signal. # Related registers: $46/CHRSC1, $47/CHSC2 PEDL86V7668-01 ML86V7668 PAL Y/C separation 2-line/3-line adaptive comb filter 2-line comb filter Trap filter ...
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... The asynchronous sampling mode, which uses an asynchronous clock directly, can be used without using PLL. # Related registers: $70/PLLC1, $71/PLLC2, $72/PLLC3, $73/PLLC4 Output Formats Register Register IOC2[ IOC2[ Control pin Register (Pins 30, 31) MODE[3:2] IOC2[5:4] (i) 4:2:2 [00] (i) 4:2:2 [01] (i) 4:2:2 [10] (i) 4:1:1 [10] (i) 4:4:4 [11] PEDL86V7668-01 ML86V7668 Register IOC2[1] [00] 0 [01]* 0 [10] 0 [10] 1 [11] 0 11/31 ...
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... MHz $01/IOC2[0] = “ 1” * Control pin Register (Pin 33) MODE[0] $00/IOC1[ PEDL86V7668-01 ML86V7668 Sampling Asynchronous $70/PLLC1[7] = “ 0” * PLL ON/line lock $70/PLLC1[7] = “ 1” PLL OFF/asynchronous Sampling clock (double-speed) Pin 46 CLKX2 27 MHz 24.545454 MHz 12/31 ...
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... For more information, contact the Phillips Corporation. Test Control Block This block is used to test the LSI chip not intended for user use standard of the Phillips Corporation. The registers patent is required to use control, but if this I PEDL86V7668-01 ML86V7668 2 C bus. 2 C-bus is used to 13/31 ...
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... Ta = 25° 25°C — — – +150 Min. Typ. — 3 3.3 — 2.25 2.5 — 3 3.3 — 3 3.3 — 3 3.3 — — 0 — — 0.8 VDD — — -0.3 — — -40 PEDL86V7668-01 ML86V7668 Rating Unit 800 °C Max. Unit 3.6 V 2.75 V 3.6 V 3.6 V 3.6 V — V VDD+0 °C 14/31 ...
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... Y[7:0], C[7:0], HSYNC L, VSYNC L, VVALID, HVALID, CLKXO, STATUS1, STATUS2, STATUS3, STATUS4, CLKX2O Min. Typ. —— 0.7VDD —— —— —— -10 —— -10 —— 1.25 1.5 —— 1.75 2 —— 0.75 1 —— —— Vrb — 0.4 PEDL86V7668-01 ML86V7668 Max. Unit —— 1.65 V 2.15 V 1.15 V Vrt V 1.3 Vp-p 15/31 ...
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... VDD 24.545454MHz VDD2 35 VDD 15 27MHz VDD2 40 24.545454MHz 30 27MHz 30 15 VDD 24.545454MHz VDD2 35 VDD 15 27MHz VDD2 40 24.545454MHz 60 27MHz 60 − PEDL86V7668-01 ML86V7668 Max. VDD = 3.6 V Unit VDD2 = 2. 110 mA 120 ...
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... CLKSEL:L —— —— CLKSEL:L —— —— CLKSEL:L —— —— CLKSEL:L —— —— CLKSEL:L —— 200 PEDL86V7668-01 ML86V7668 Max. Unit — MHz — MHz — ...
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... GND CLKX2 RESET_L (*) Output data is “ don’ t care” at reset. CLKSEL tcxd21 tcxd11 s data sheet Setup Time Valid Clock rst_w Don’t Care PEDL86V7668-01 ML86V7668 tclkx2 tr tcxd22 tcxd22 tcxd21 tcxd21 Tod21 Tod2x2 Todx21 Tod22 Tod2x22 Todx22 Tod23 Tod2x2 Todx23 ...
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... C-bus timing is based on the table above ACK t C_SCL Change of Data Allowed tF tHD:STA S tHIGH tSU:DAT tSU:STA Min. 0 4.7 4.0 4.7 4.0 4.7 300 250 4.7 PEDL86V7668-01 ML86V7668 ACK 3-8 Stop Condition P tSU:STO Typ. Max. Unit 100 400 KHz s s s s s 1 300 ns ...
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... Vertical Sync Signals (NTSC 624 625 312 313 314 315 316 317 318 Vertical Sync Signals (PAL) PEDL86V7668-01 ML86V7668 283 284 285 319 336 337 338 20/31 ...
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... In the FIFO mode, the output cycle is fixed, so the delay varies. In the PAL mode, where Y/C separation is performed by trap filter not added. Data delay Blank HSYNC delay Absorption difference Pixel rate, = FIFO Input signal FIFO/FM mode Composite FIFO-1 Composite FM Composite FIFO-1 Composite FM PEDL86V7668-01 ML86V7668 Active Data Delay 1.5H 1.5H 1.5H 1.5H 21/31 ...
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... Odd/20 Even/20 118 140 640 780 Odd/24 132 144 720 864 Even/25 PEDL86V7668-01 ML86V7668 60 pixels Total line Active line (VVALID = H) V Active Total line VSYNC_L line Odd/262 Odd/242 Odd/262 Even/243 Even/263 Even/263 Odd/312 Odd/288 Odd/312 Even/313 ...
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... Each VALID signal and the ODD/EVEN signal are selected by the STATUS signal. VSYNC_L, ODD/EVEN HSYNC_L VSYNC_L 1 pixel ODD/EVEN ODD (STATUS) VSYNC_L ODD/EVEN (STATUS) VALID Signal HSYNC_L 60 pixels Back Front HVALID porch porch 2 pixels VVALID 60pixels 1 pixel EVEN PEDL86V7668-01 ML86V7668 0 pixel 23/31 ...
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... Y/CbCr (8 bits ( bits (CbCr) (4:2:2) / (4:1:1)) CLKX2O CLKXO HVALID Y[7:0] Y-1 Y0 C[7:0] Cr-2 Cb0 18-bit RGB (6 bits ( bits ( bits (B)) CLKX2O CLKXO HVALID G [5:0] G [5:0] B [5:0] R-1 R0 Cr0 Y1 Cb2 Y2 Cr2 Crn-3 Yn-2 Cbn-1 Yn-1 Crn Cr0 Cb2 Cr2 PEDL86V7668-01 ML86V7668 Cbn+1 Yn-1 Yn Cbn Crn Gn-1 Gn Bn-1 Bn Rn-1 Rn 24/31 ...
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... Video data block 1440T(PAL/NTSC) Multiplexed video data Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y4 ------- Cr718 Y719 4T Digital line Total pixels Active pixels SAV: Start of active video timing reference code EAV: End of active video timing reference code T: clock periods 37ns normal (1/27MHz) PEDL86V7668-01 ML86V7668 60 pixels 25/31 ...
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... PEDL86V7668-01 ML86V7668 HEX LSB [1] [ ...
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... PEDL86V7668-01 ML86V7668 HEX LSB [2] [1] [ ...
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... Before using the decoder, please carefully evaluate and consider the signal conditions and usage environment of the intended use. In addition to this Data Sheet, a ML86V7668 User's Manual is also available. The User's Manual explains each register and provides examples of adapted circuits as well as other information helpful in the design phase. Please read the User's Manual before embarking on design work ...
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... The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’ s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). PEDL86V7668-01 ML86V7668 (Unit: mm) 29/31 ...
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... OKI Semiconductor REVISION HISTORY Document No. Date PEDL86V7668-01 Aug. 28, 2004 Page Previous Current Edition Edition – – Preliminary edition 1 PEDL86V7668-01 ML86V7668 Description 30/31 ...
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... The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these part of the contents contained herein may be reprinted or reproduced without our prior permission. PEDL86V7668-01 ML86V7668 Copyright 2005 Oki Electric Industry Co., Ltd. 31/31 ...