ml87v5002 Oki Semiconductor, ml87v5002 Datasheet

ml87v5002

Manufacturer Part Number

ml87v5002

Description

Audio Delay Ic With Built-in 2-mbit Dram

Manufacturer

Oki Semiconductor

Datasheet

1.ML87V5002.pdf (36 pages)

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GENERAL DESCRIPTION

The ML87V5002 has been developed for solving “Lip-sync problems” in DVD systems, hard disc recording

devices, digital TVs and Home Theater Systems. The ML87V5002 can delay the digital audio signal of each of

eight channels by setting each register. The ML87V5002 is suitable for synchronizing sounds with motions when

loads are too heavy for DSP to control audio delay.

The ML87V5002 does not require any external memory for the audio delay because the ML87V5002 has a built-in

2-Mbit DRAM. The maximum delay time is, for example, 341.3 ms at 48 kHz in 8-ch mode and 1.365 sec at 48

kHz in 2-ch mode. Supporting two to eight audio channels; the ML87V5002 is suitable for applications ranging

from simple stereo systems to multi-channel systems. The granularity of the delay time is the sampling period, or

Ts. The delay time of each channel can be set in steps of Ts.

The ML87V5002 interfaces to most audio LSIs since the ML87V5002 supports general digital audio formats, such

as I

input and output formats.

FEATURES

• Digital audio delay control: The digital audio signals input from the DI0-DI3 pins are delayed for specific

• No external memory: No external memory is required for the delay because the 2-Mbit DRAM is included.

• Three digital-audio formats: I

• Input/output format settings: I

• Data bit lengths: 16/20/24/32 bits

• Wide range sampling frequencies: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, and 192 kHz

• Maximum audio delay time:

• Standard host interface: I

• Minimum delay time step: The granularity of delay time is Ts.

• Independent delay time setting: The delay time of each channel can be set.

• General power supply voltage: 3.3 V 0.3V

• 5V tolerant I/O: Audio interface inputs, I

• Package:

Note:

• System clock requirements

OKI Semiconductor

ML87V5002

Audio Delay IC with Built-in 2-Mbit DRAM

delay times set by an external device and are output from the DO0-DO3 pins.

and output formats.

The maximum delay time (when the audio data length is 16 bits)

32-pin plastic TSOP type I (TSOP(1)32-P-0814-0.50-1K)

- Frequency

- Phase

S, right justified, and left justified. In addition, suitable digital audio formats can be selected as each of the

- 1.365 sec

- 682.5 ms

- 341.3 ms

- 170.7 ms

- 85.3 ms

The frequency of the system clock should be 128 times the sampling frequency or more. When the

sampling frequency is 192 kHz, be sure to set the system clock frequency at 128 times the sampling

frequency.

The system clock should be synchronized with LRCK and the BCK. In synchronized condition, the phase

variation is acceptable.

(48 kHz, 2-ch mode)

(96 kHz, 2-ch mode)

(192 kHz, 2-ch mode)

(48 kHz, 8-ch mode)

(96 kHz, 8-ch mode)

(192 kHz, 8-ch mode)

C slave interface is supported.

S, right justified and left justified formats.

S, right justified, or left justified format can be selected as each of the input

C, and INT are tolerant to 5 V.

Issue Date: Sep. 1, 2005

FEDL87V5002-01

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