msm7617-001 Oki Semiconductor, msm7617-001 Datasheet - Page 7

• Manufacturer Part Number: msm7617-001
• Description: 2-channel Echo Canceler
• Manufacturer: Oki Semiconductor

PIN DESCRIPTIONS (Continued)
OKI Semiconductor
Pin
16
17
18
19
Symbol
SOUT1
RST1
ATT1
HD1
Type
O
I
I
I
Reset signal input pin for channel 1.
“L”: Reset
“H”: Normal operation
Input signals are invalid for 100 s after reset (after RST returns to “H” from “L”) for
setting initial values.
Input the base clock during reset. Output pins will be placed in the following states
during reset.
Hi-Z: ROUT1, SOUT1
No effect: SYNCO, SCKO, ROUT2, SOUT2, DF2, WDT2
Previous state: DF1, WDT1
At power-up, keep this pin to "L" longer than 1 s after a master clock (CLKIN) gets
stably supplied, and execute initialization of LSI internal registers by releasing it to
"H".
Also such as in a case when this LSI is intended to be kept in reset state, for
instance, till the first call comes in, the above-mentioned initialization of LSI internal
registers must be done, and, later than 560ns since the initialization, assert this pin
back to "L" and wait the call.
Howling detection control pin for channel 1.
This pin controls detection and canceling of howling generated by the acoustics of
handsfree telephone.
“L”: Howling detector on
“H”: Howling detector off
ATT control pin for channel 1.
This pin controls the ATT function for preventing howling with the attenuators
(ATT) provided on RIN and SOUT. When input is only on RIN, the SOUT
attenuator is activated. When there is no input on RIN or there is input on both SIN
and RIN, the RIN input attenuator is activated. Either the ATT for the RIN output or
the ATT for the SOUT is always activated in all cases, and the attenuation of ATT is
6 dB.
“H”: Attenuator off
“L”: Attenuator on
Because the attenuator is inserted opposite the speaker, it is effective for further
reducing echo.
PCM data output pin. Output signal changes depending on the setting of the IOM
pins (refer to the block diagram).
Data is always output on the rising edge of SCK. This pin is put in high impedance
state while there is no data or during reset.
In 2-channel parallel I/O mode, this pin becomes SOUT for channel 1 and outputs
the PCM signal synchronous with SYNC1. In 2-channel serial I/O mode, this pin
outputs the SOUT signal as a multiplexed PCM signal of SOUT signal for channel
1 and channel 2 synchronous with SYNC1.
In 1-channel cross-connected mode, this pin becomes high impedance.
Description
MSM7617
7