msm7652 Oki Semiconductor, msm7652 Datasheet
msm7652
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msm7652 Summary of contents
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... Y, R-Y, B-Y signals. For the scanning system, interlaced or noninterlaced mode can be selected. Since the MSM7652 is provided with pins dedicated to overlay function, text and graphics can be superimposed on a video signal. In addition, this encoder has an internal 10-bit DAC. So, when compared with using a conventional analog encoder, the number of components, the board space, and points of adjustment can greatly be reduced, thereby realizing a low cost and high-accuracy system ...
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... MSM7652 APPLICATIONS • Video CD • Video game equipment • Electronic still cameras • Video file systems • Video cameras • Videophones • Multimedia equipment • Video printers • Videoconferencing systems • Scanners • Video graphics boards 2 ¡ Semiconductor ...
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RESET_L OLC OLR YUV color OLG Generator OLB Y Level converter YD[7:0] U Level Prologue converter CD[7:0] Block V Level converter VSYNC_L HSYNC_L Sync Generator & Timing Controller BLANK_L CLKX2 SEL[2:1] MS MODE CLKX1O CLKSEL Black & Blank Pedestal Overlay ...
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... MSM7652 PIN CONFIGURATION (TOP VIEW SDA 3 SCL 4 ADRS 5 RESET_L 6 MODE 7 OLC 8 OLR 9 OLG 10 OLB 11 CLKX1O 12 OUTSEL No-connection pin 56-Pin Plastic QFP ¡ Semiconductor SEL2 40 SEL1 39 CLKSEL 38 CD0 37 CD1 36 CD2 35 CD3 34 CD4 33 CD5 32 CD6 31 CD7 ...
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... V digital power supply Clock input pin (27 MHz) 8bit digital image chrominance signal data input pins (13.5 MHz mode). Level conforms to ITU-601. Fixed to "0" for ITU Rec. 656, 27 MHz-YCbCr mode. Operation mode select pin. "0" MHz mode / "1" : 13.5 MHz mode. MSM7652 5 ...
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... MSM7652 PIN DESCRIPTIONS (2/2) Pin I/O Symbol 40 I SEL1 41 I SEL2 DGND 44 I TEST1 45 I TENB 46 I/O VREF COMP 49 AGND CVBSO 53 AGND DGND 6 Description Enable pin. Normally fixed to "0". Sleep mode "1" with TEST1 = "0" ...
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... 3 output load = 37 3 Vrefex — 25˚C Riadj (*2) — R (*3) — L and MSM7652 Rating Unit –0.3 to +4.5 V –0.3 to +4.5 –0 600 mW –55 to +150 °C Typ. Max. Unit 3.3 3.6 V 3.3 3.6 — — V — 0 ˚C ...
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... MSM7652 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter "H" Level Output Voltage "L" Level Output Voltage Input Leak Current Output Leak Current Power Supply Current (operating) Power Supply Current (standby) Power Supply Current (Sleep mode C-bus SDA Output Voltage 2 I C-bus SDA Output Current ...
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... C-bus basic input/output timing. SDA MSB SCL Start Condition Data Line Stable: Data Valid Change of Data Allowed 2 I C-bus Basic Input/Output Timing TS ts1 Invalid data th1 td1 valid data td2 ACK t t L_SCL H_SCL t C_SCL MSM7652 9 P 3-8 ACK Stop Condition 9 ...
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... MSM7652 BLOCK FUNCTIONAL DESCRIPTION 1. Prologue Block This block separates input data at the ITU Rec.656 format into a luminance signal (Y) and a chrominance signal (Cb & Cr), and also generates information concerning sync signals HSYNC_L, VSYNC_L, and BLANK_L. This block separates input data at the 27 MHz YCbCr (8-bit input) format into a luminance signal (Y) and a chrominance signal (Cb & ...
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... Interpolation Filter (IPF) This block performs upsampling at CLKX2 for luminance signals and chrominance signals modulated with CLKX1 divided from CLKX2. Interpolation processing is executed in this process. • Closed Caption Block This block generates the signal for closed caption standard of Phillips Corporation. MSM7652 11 ...
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... MSM7652 INPUT DATA FORMAT The signal level specified by the ITU601 is input. When other signal levels than specified by the ITU601 are input, the luminance signal level is clipped 254 and the chrominance signal level 254. For chrominance signal input, the offset binary and 2's complement formats are available by setting of internal registers ...
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... RELATIONSHIP BETWEEN BLANK SIGNAL AND INPUT IMAGE DATA The blank signal is generated by the ITU Rec.656 standard input data. The input image data is valid when the blank signal is "H". Cb0 Y00 Cr0 Y01 Cb1 Y10 Cr1 Y11 VALID DATA Input Timing MSM7652 EAV(1st) EAV(2nd) EAV(3rd) EAV(4th) don't care 13 ...
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... MSM7652 VALID DATA RANGE According to the ITU Rec.656 standard, the pixel data immediately from SAV (4th word fixed value before EVA is valid. The following figure shows the relationship between the input data at the CCIR Rec.656 format and the sync, luminance, chrominance signals which are processed inside the encoder. ...
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... VALID DATA Video data input timing are the same bit ( bit (CbCr) mode START In slave mode t (Ts) Operation mode STA 250 ITU 601 NTSC 280 ITU 601 PAL MSM7652 don't care period. ACT t (Ts) STA 260 290 15 ...
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... MSM7652 Timing of Input Data to HSYNC_L CLKX2 CLKX1O HSYNC_L OLR,OLG, OLB, OLC Invalid Data YD Invalid Data Input Timing when BLANK_L is Input CLKX2 BLANK_L YD Input timing at 27 MHz in YCbCr format Timing of Input Data to HSYNC_L CLKX2 CLKX1O HSYNC_L OLR,OLG, OLB, OLC Invalid Data YD Invalid Data ...
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... Internal Synchronization Output Timing Input and output timing of HSYNC_L and VSYNC_L in master mode is as follows. CLKX2 HSYNC_L VSYNC_L Output timing of internal synchronization, HSYNC_L and VSYNC_L VSYNC_L YA 523 524 Output timing of internal synchronization VSYNC_L t d1 525 MSM7652 ...
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... MSM7652 OUTPUT FORMAT The timing conforms to the ITU624 standard. In the NTSC operation mode, the existence/non-existence of setup level is selected by setting of internal regsiters. Data level on the DAC input terminal: When the contents of 100% luminance order color bar are input into the encoder, the input level is as follows ...
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... NTSC Y Signal Output (Setup 0) C Wave Form (NTSC) DAC data Lumi (IRE) 858 63 836 59 754 44 622 20 512 0 402 –20 Color Burst 270 –44 188 –59 166 –63 White Cyan Magenta Yellow Green Yellow Green Cyan Magenta NTSC C Signal Output MSM7652 Blue Red Black Red Blue 19 ...
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... MSM7652 Composite Wave Form (PAL) DAC data Lumi (IRE) 973 133 792 100 731 89 627 70 566 59 467 41 406 30 359 21.5 302 11 241 0 123 –21.5 4 –43 Y Wave Form (PAL) DAC data Lumi (IRE) 792 100 731 89 627 70 566 59 467 41 406 30 302 11 241 0 4 –43 ...
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... Semiconductor C Wave Form (PAL) DAC data Lumi (IRE) 858 63 836 59 754 44 630 21.5 512 0 394 –21.5 Color Burst 270 –44 188 –59 166 –63 Yellow Green Cyan Magenta PAL C Signal Output MSM7652 Red Blue 21 ...
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... MSM7652 NTSC (Interlaced) Field 1 Reference sub-carrier phase 259 260 261 262 263 A Field 2 Reference sub-carrier phase 259 260 261 262 263 A Field 3 Reference sub-carrier phase 259 260 261 262 263 A Field 4 Reference sub-carrier phase 259 260 261 262 263 A Output timing (Interlaced NTSC) ...
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... First equalizing pulse period (3H) B Vertical synchronization period (3H) C Second equalizing pulse period (3H) D Burst pause period E Vertical blanking period (20H) Output timing (Interlaced NTSC) MSM7652 Period Odd field (Even field) 259.5 to 262. 6,259.5 to 262. 17,259.5 to 262.5H 23 ...
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... MSM7652 NTSC (Non-interlaced) Continuous Odd Field Reference sub-carrier phase 260 261 262 A Reference sub-carrier phase 260 261 262 A Continuous Even Field Reference sub-carrier phase 260 261 262 A Reference sub-carrier phase 260 261 262 A Output timing (Non-interlaced NTSC) Symbol Name First equalizing pulse period (2H) ...
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... Period Field 1,5 Field 2,6 311 to 312.5H 311 to 312. 2. 2. 6,310 to 312. 5.5,308.5 to 312. 22.5,311 to 312. 22.5,311 to 312.5H MSM7652 Field 3,7 Field 4,8 311 to 312.5H 311 to 312. ...
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... MSM7652 PAL (Non-interlaced) Continuous Odd Field 309 310 311 312 1 A 309 310 311 312 1 A Continuous Even Field 309 310 311 312 1 A 309 310 311 312 1 A Output timing (Non-interlaced PAL) Symbol Name A First equalizing pulse period (2H) B Vertical synchronization period (2.5H) C Second equalizing pulse period (2 ...
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... Horizontal blanking period 31Ts 71Ts 127Ts 838Ts 31Ts 75Ts 142Ts 844Ts MSM7652 1/2H 31Ts 365Ts 64Ts 429Ts 32Ts 369Ts 63Ts 432Ts Total dots/1H 858 864 27 ...
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... MSM7652 Setup Level Setting When the NTSC operation mode is selected, one of the two kinds of setup level can be selected by setting of registers. When the setup level 0 is selected, the Black-to-White is 100IRE. When the setup level 7.5IRE is selected, the Black-to-White is 92.5IRE. However, this setup function is valid only for the NTSC mode and invalid for the PAL mode. ...
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... The input timing is shown below. SDA MSB SCL Start Condition Data Line Stable: Data Valid Change of Data Allowed 2 I C-bus Basic Input/Output Timing A Data 0 A ..... Description ACK 3 L_SCL H_SCL t C_SCL MSM7652 Data ACK Stop Condition 29 ...
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... MSM7652 CLOSED CAPTION FUNCTION The closed caption function based on the NCI standard is available. The caption information on each line is multiplexed as a 26-cycle signal which is synchronized at 503 kHz. Each cycle is described below. Cycles Clock-Run-in period Cycles Start Code Cycles Caption Information The output timing when data is multiplexed by the closed caption function is shown below ...
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... Interlace Scanning method *0 : Interlace 1 : Non-interlace Color bar Adjusting luminance order color bar output control *0 : Input image data or overlay data 1 : Luminance order color bar Overlay level Overlay signal/adjusting luminance order color bar output level control 75% *11 : 100% MSM7652 Description 31 ...
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... MSM7652 Sub- Default Register name R/W address value CCEN Write 02 00 CCEN[0] Only CCLN Write 03 11 CCLN[4:0] Only CCODT0 Write 04 00 CCODT0[7:0] Only CCODT1 Write 05 00 CCODT1[7:0] Only CCEDT0 Write 06 00 CCEDT0[7:0] Only CCEDT1 Write 07 00 CCEDT1[7:0] Only CCSTAT Read CCSTAT[0] ...
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... The following shows the characteristics when the clock frequency is 27 MHz. 0 –20 –40 –60 –80 –100 Sampling Filter Frequency Characteristic (Note) The characteristics of these filters are based on design data Frequency [MHz Frequency [MHz] MSM7652 ...
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... LPF (Toko-make 621LJN-1471 is recommended.) Note: The termination converter analog output with a 37.5 W load eliminates need for an AMP 3 3 REF FS COMP YA MSM7652 CVBSO CA DGND AGND CLKX2 +AVCC 0 3.6 mH – 150 W 560 W 164 pF 560 W 0.1 mF – ...
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... Semiconductor PACKAGE DIMENSIONS 56-Pin Plastic QFP MSM7652 (Unit : mm) 35 ...
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... MSM7652 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product ...