msm7664 Oki Semiconductor, msm7664 Datasheet - Page 51

• Manufacturer Part Number: msm7664
• Description: Ntsc/pal Digital Video Decoder
• Manufacturer: Oki Semiconductor

¡ Semiconductor
ADC register 3 (ADC3)
Note:
0 level detect register (ZLD)
Note:
Default
Recommended Value
Default
Recommended Value
ADC3[7]
ADC3[6:4]
ADC3[3]
ADC3[2:0]
ZLD[7:3]
ZLD[2:0]
Register Name
Register Name
These registers determine the analog gain control decision level. The stability can be
obtained from higher values.
These registers decide the continuance of sync tip level and its result is reflected in AGC
gain. The stability can be obtained from higher values.
Undefined
ADC gain control margin level select
Undefined
ADC gain control line select
Undefined
0 level detect width (¥ 8 pixels)
ADC3[7] ADC3[6] ADC3[5] ADC3[4] ADC3[3] ADC3[2] ADC3[1] ADC3[0]
ZLD[7]
0
0
0
0
ZLD[6]
101, 110, 111: Undefined
101, 110, 111: Undefined
0
0
0
0
Write only
Write only
ZLD[5]
*010: 40 mV
*010: 4 lines
*010: 16 pixels
000: 10 mV
001: 20 mV
011: 80 mV
100: 160 mV
000: 1 line
001: 2 lines
011: 8 lines
100: 16 lines
000: Undefined
001: 8 pixels
011: 24 pixels
100: 32 pixels
101: 40 pixels
110: 48 pixels
111: 56 pixels
1
1
0
0
Set to 0
Set to 0
Set to 0
ZLD[4]
0
0
0
0
<address: $13>
<address: $14>
ZLD[3]
0
0
0
0
ZLD[2]
0
0
0
0
ZLD[1]
PEDL7664-01
1
1
1
1
MSM7664
ZLD[0]
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0
0
0
0