msm7582b Oki Semiconductor, msm7582b Datasheet
msm7582b
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msm7582b Summary of contents
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... GENERAL DESCRIPTION The MSM7582/7582B are CMOS ICs for the p/4 shift QPSK modem developed for the digital cordless telephone systems. The devices are designed for Personal and Cell station applications, the MSM7582B is the improved MSM7582 in modulator burst rise-up and fall-down characteristics. FEATURES • ...
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PDN0 PDN1 PDN2 IFIN Phase Detector Delay Detector IFSEL0 MCK S (From CR) E IFCK L IFSEL1 (From CR) Decoder To each block each DEN block EXCK Control DIN Register (CR) DOUT ± ...
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Semiconductor PIN CONFIGURATION (TOP VIEW) AGND I– Q– ENV 7 PDN0 8 PDN1 9 10 PDN2 SLS1 12 SLS2 13 14 RCW AFC 15 RPR 16 32-Pin ...
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... The transmit timing signal for the burst data is input to the device pin. If TXW is “1”, the modulation data is output. However, the MSM7582 is different from the MSM7582B in the ramp response time for burst rise-up and burst fall-down modulated outputs, as shown in the table below ...
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Semiconductor MSM7582 (1) CR0 – "0" TXD D10 D11 D12 D13 TXCI (384 kHz) TXW TXCO (384 kHz Ramp rise-up 1.75 ...
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... Semiconductor MSM7582B (1) CR0 – "0" TXD D10 D11 D12 D13 TXCI (384 kHz) TXW TXCO (384 kHz Ramp rise-up 2 symbols Delay of 6.25 symbols (2) CR0 – "1" TXD D10 D11 D12 D13 TXCI (3 ...
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Semiconductor ENV Quadrature modulation signal envelope ( Its output level is 500 mV with 1.6 Vdc as a center value. The output pin load conditions are kW pF. The gain of this output ...
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Semiconductor MCK Master clock input. The clock frequency is 19.2 MHz. IFIN Modulated signal input for the demodulator block. Select the IF frequency from 1.2 MHz, 10.7 MHz, 10.75 MHz, and 10.8 MHz, based on CR0 – B4 and ...
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Semiconductor SLS2, SLS1 Receiver slot select signal inputs. The devices have four sets of clock recovery circuit to each channel and four AFC information storage registers. One these circuits is selected from a combination of the signals at these ...
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... Serial control ports for the microprocessor interface. The MSM7582 and MSM7582B contain a 6-byte control register. An external CPU uses these pins to read data from and write data to the control register. DEN is an enable signal input pin. EXCK is a data shift clock pulse input pin. DIN is an address and data input pin. DOUT is a data output pin ...
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Semiconductor The register map is shown below Table-2 Control Register Map Address Register CR0 PS/CS TXCSEL Ich CR1 GAIN3 GAIN2 ENV CR2 GAIN3 GAIN2 Ich CR3 ...
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Semiconductor ABSOLUTE MAXIMUM RATINGS Parameter Symbol Power Supply Voltage V Digital Input Voltage V Operating Temperature T T Storage Temperature STG RECOMMENDED OPERATING CONDITIONS Parameter Symbol Power Supply Voltage V Operating Temperature Range Ta Input High Voltage V Input ...
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Semiconductor Analog Interface Characteristics Parameter Symbol Output Resistance Load R Output Capacitance Load C V DC1 V DC2 V DC3 Output DC Voltage Level V DC4 V DC5 V DC6 Output AC Voltage Level V DCVL Output DC Voltage ...
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Semiconductor Digital Interface Characteristics Parameter Symbol t t Transmitter Digital t Input/Output Setting Time t XD1 t XD2 t XD3 t XD4 t RD1 t RD2 Receiver Digital Input/Output t RS1 Setting Time t RS4 ...
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Semiconductor TIMING DIAGRAM Transmit Data Input Timing TXCI [TXCO (384 kHz) SX TXW TXD Transmit Clock (TXCO) Output Timing (when CR0 – TXCI 1 2 ...
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Semiconductor SLS1 SLS2 RCW AFC RPR RXC t RD1 RXD Figure 7 Receiver (Demodulator) Digital Input/Output Timing DEN EXCK DIN W/R A2 DOUT Figure 8 Serial Control Port Interface ...
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Semiconductor FUNCTIONAL DESCRIPTION Control Registers (1) CR0 (basic operation mode setting CR0 PS/CS TXC SEL Initial value (*) the initial value is set when a reset signal is supplied by a PDN. B7: PS/CS ...
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Semiconductor (2) CR1 (I, Q gain adjustment Ich Ich CR1 GAIN3 GAIN2 Initial value B4: I+/I– output gain setting steps (Refer to Table-3 B0: Q+/Q– output gain setting, ...
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Semiconductor (4) CR3 (I– output offset voltage adjustment Ich Ich CR3 Offset4 Offset3 Initial value B3: I– output pin offset voltage adjustment (Refer to Table-4 B0: Not used (5) CR4 (Q– ...
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Semiconductor (6) CR5 B7 B6 BSTO CR5 ICT6 ENBL Initial value 0 0 B7: Modulator burst window output enable bit. 1/The timing of the I and Q baseband modulation output burst is output at the TXCO pin. 0/The 384 ...
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Semiconductor State Transition Time Note: The transition time less unless otherwise stated Standby mode (PDN0 = 0) Communication mode (PDN0 = Mode E PDN1 = 1 PDN2 = Figure ...
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Semiconductor APPLICATION CIRCUIT AGND Modulator I component output 4 I– Modulator Q component output 6 Q– 7 ENV 8 PDN0 9 PDN1 10 PDN2 11 Power-down ...
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Semiconductor Demodulator Control Timing Diagram (Example Democulator unit Slot 1 Modulator G R1 input data Timing ...
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Semiconductor PACKAGE DIMENSIONS TSOPI32-P-814-0.50-1K Mirror finish Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and ...