msm9841 Oki Semiconductor, msm9841 Datasheet - Page 4

• Manufacturer Part Number: msm9841
• Description: Recording And Playback Lsi With Built-in Fifo Msm9841record/playback Ic With Built-in Fifo Data Sheet
• Manufacturer: Oki Semiconductor

¡ Semiconductor
PIN DESCRIPTIONS
FUL/DREQR
CH/DACKR
Symbol
D15-D8
DREQL
DACKL
D7-D0
BUSY
EMP
MID
WR
D/C
RD
CS
Type
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
For 8-bit bus interface, the command allows these pins to be configured to be inputs or outputs
to input or output data to and from an external memory. Otherwise, these pins are configured
to be inputs only.
For 16-bit interface, these pins are a bidirectional data bus to input or output data to and from
an external microcontroller and memory.
Birirectional data bus to input or output data and output status to and from an external
microcontroller and memory.
Write pulse input pin. This pin pulses "L" when command or voice data is input to D15-D0 pins.
Read pulse input pin. This pin pulses "L" when status or voice data is output to D15-D0 pins.
Accepts write pulse and read pulse when this pin is "L". Does not accept write pulse and read
pulse when this pin is "H".
Voice data is input or output to and from D15-D0 pins when this pin is "H". Command is input
to and status is output from D7-D0 pins when this pin is "L".
This pin outputs a "L" level during RECORDING, PLAYBACK or PAUSE.
"H" level indicates that there is no data in FIFO memory. Active "H" can be changed to active "L"
by command input.
"H" level indicates that more than half of the FIFO memory space is filled with data.
During playback, voice synthesis starts when MID changes to "H" level. Active "H" can be
changed to active "L" by command input. This pin outputs a synchro signal for voice data input/
output when non-use of FIFO is selected.
"H" level indicates that FIFO memory is full of data. During playback, this pin is "H" and data
cannot be written in FIFO memory. Active "H" can be changed to active "L" by command input.
When DMA transfer and stereo playback are selected, "H" level DREQR outputs a signal to
request a DMA transfer. Active "H" can be changed to active "L" by command input.
When stereo playback is selected and CH is "H", the EMP, MID or FUL pin outputs the status of
right FIFO memory. When CH is "L", the EMP, MID or FUL pin outputs the status of left FIFO
memory. Set this pin to "L" during recording and monophonic playback. When DMA transfer
and stereo playback are selected, DACKR is selected. In this case, input a DMA transfer
acknowledge signal to DACKR. When DACKR is "L", the IOW signal is accepted. Active "L" can
be changed to active "H" by command input.
When DMA transfer is selected, "H" level DREQL outputs a signal to request a DMA transfer.
When stereo playback is selected, "H" level DREQL outputs a signal to request a DMA transfer.
Active "H" can be changed to active "L" by command input.
Input to DACKL a signal when DMA transfer is permitted by the DMA controller. When DACKL
is "L", IOR and IOW signals are accepted. When stereo playback is selected, input to DACKL a
DMA transfer acknowledge signal for left FIFO memory. Active "L" can be changed to active "H"
by command input. If DMA transfer is not used, set this pin to "H" level.
Description
FEDL9841-04
MSM9841
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