msm9201-01 Oki Semiconductor, msm9201-01 Datasheet - Page 16

• Manufacturer Part Number: msm9201-01
• Description: Fluorescent Display Tube Controller Driver
• Manufacturer: Oki Semiconductor

¡ Semiconductor
Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to "Low" level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rise of the shift clock, which
is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated
and data is written to each register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin
changes from "High" to "Low" is recognized in 8-bit units.
When data is written to DCRAM* Command and address data
* When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are
Reset Function
Reset is executed when the RESET pin is set to "L", (when turning power on, for example,) which
initializes all functions.
The initial status is as follows.
• Address of each RAM .................. address "00"H
• Data of each RAM ........................ All contents are undefined
• General output port ..................... All general output ports go "Low"
• Number of display digits ............ 24 digits
• Contrast adjustment ..................... 8/16
• All display lights ON or OFF ..... OFF mode
• Segment output ............................ All segment outputs go "Low"
• AD output ..................................... All AD outputs go "Low"
After reset is executed, perform settings again according to "Initial Setting Flowchart" shown
later.
internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later
bytes.
CS
CP
DA
B0
LSB
B1 B2 B3 B4 B5 B6 B7
1st byte
MSB
t
DOFF
LSB
B0 B1 B2 B3 B4 B5 B6 B7
Character code data
2nd byte
MSB
B0 B1 B2 B3 B4 B5 B6 B7
LSB
Character code data of the
next address
2nd byte
PEDL9201-03
MSM9201-01
MSB
t
CSH
16/35