ml7084-001 Oki Semiconductor, ml7084-001 Datasheet - Page 32

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ml7084-001

Manufacturer Part Number
ml7084-001
Description
4ch Voip Codec
Manufacturer
Oki Semiconductor
Datasheet
These are the pins for either connecting the crystal oscillator for the master clock or for inputting an external master
The oscillations of the master clock oscillator will be stopped during a power down due to the PDNB signal. The
This is the power down control input pin. The power down stateis entered when this pin goes to “0”. In addition, this
See Figure 1 for the timings of PDNB, AVREF, and XO.
Note:
At the time of turning on the power, start from the power down state using PDNB.
clock signal.
oscillations start when the power down condition is released, and the internal clock supply of the LSI will be started
after counting up the oscillation stabilization period (of about 10 ms), and the DSP firmware can then be downloaded.
Examples of crystal oscillator connection and external master clock input are shown in Figure. 11.
pin also has the function of resetting the LSI. In order to prevent wrong operation of the LSI, carry out the initial
power-down reset after switching on the power using this PDNB pin. Also, keep the PDNB pin at “0” level for 250
μs or more to initiate the power down state.
XI, XO
PDNB
Also, if used by inputting a master clock to the XI pin, maintain a power down state (PDNB = 0) until the digital
power (DVDD[6:0]) and analog power (AVDD[1:0]) are supplied (90% or more), as well as until a master clock is
completely input to the XI pin, and then cancel the power down state (PDNB = 0→1). Even in this case, fix PDNB at
“0” for at least 250 μsec.
OKI Semiconductor
PDNB
C1
XI
Figure 11 Examples of Oscillator Circuit and Clock Input
Crystal
R
C2
XO
To internal
circuits
HC-49/U-S [C
Kyocera Kinseki Corp.
Crystal (12.288 MHz)
PDNB
L
= 12 pF]
XI
12.288 MHz
8pF
C1
FEDL7224-001FULL-01
8pF
C2
XO
Open
ML7224-001TC
To internal
circuits
1MΩ
R
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