ak4145 AKM Semiconductor, Inc., ak4145 Datasheet - Page 10

• Manufacturer Part Number: ak4145
• Description: Digital Stereo Btsc Encoder
• Manufacturer: AKM Semiconductor, Inc.

■
After setting the PDN pin “L” to “H”, the AK4145 remains in power-down mode until the input of LRCK= “↑” after
MCLK. If the MCLK and LRCK are provided, the AK4145 exits the reset state, power-on the voltage reference circuit,
and the PLL will be locked. The output signal is masked until when the PLL locks to the MCLK (also RSTN bit = “1” is
required in serial mode).
Note:
■
The external clocks required to operate the AK4145 are MCLK, LRCK and BICK. The AK4145 supports 256fs, 384fs,
512fs and 768fs as master clock (MCLK). The AK4145 should be reset by the PDN pin = “L” after these clocks are
provided. After exiting reset by the PDN pin = “H”, the AK4145 remains in power-down mode until the input of LRCK=
“↑” after MCLK.
Rev. 0.3
When changing the sampling rate, the PLL lock signal and BTSC encoder are initialized. The output is muted until the
PLL re-locks.
Power-on Sequence
System Clock
AVDD
TVDD
AVDD
PDN (I)
MCLK (I)
LRCK (I)
(PLL: Internal)
(PLL Lock: Internal)
CA (O)
32.0kHz
44.1kHz
48.0kHz
fs
Power off
Fix the pin setting
11.2896MHz
12.2880MHz
8.1920MHz
256fs
Power on
12.2880MHz
16.9344MHz
18.4320MHz
CA=VCOM=VSS
384fs
Table 4. System clock example
Figure 5. Power-on Sequence
MCLK
16.3840MHz
22.5792MHz
24.5760MHz
(1)
512fs
- 10 -
CA=VCOM≅AVDD/2
(1) Waiting the MCLK&LRCK. PLL=free run
(2) PLL Locking Time
(3) Data output is Muted
· · ·
33.8688MHz
36.8640MHz
24.576MHz
(3)
768fs
(2)
2.0480MHz
2.8224MHz
3.0720MHz
64fs
Normal Operation
BICK
4.0960MHz
5.6448MHz
6.1440MHz
128fs
[AK4145]
2007/11