ak4104 AKM Semiconductor, Inc., ak4104 Datasheet - Page 14

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ak4104

Manufacturer Part Number
ak4104
Description
192khz 24-bit 3.3v Dit
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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The AK4104 can select 4-wire μP I/F mode (MODE bit = “0”) or 3-wire μP I/F mode (MODE bit = “1”).
1.4-wire Serial mode (MODE bit = “0”, default)
The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI and CDTO. The
data on this interface consists of Chip address (2bits, C1/0; fixed to “11”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data are clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. CSN should be set to “H” once after the 16th CCLK. For read operations, the CDTO output goes high
impedance after a low-to-high transition of CSN. The maximum speed of CCLK is 5MHz. PDN pin = “L” resets the
registers to their default values.
*When the AK4104 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
MS0642-E-00
register is inhibited.
μP Control Interface
WRITE
READ
CCLK
CDTO
CSN
CDTI
CDTI
CDTO
C1-C0: Chip Address: (Fixed to “11”)
R/W:
A4-A0: Register Address
D7-D0: Control Data
C1
C1
READ/WRITE (0:READ, 1:WRITE)
0
C0
C0
1
Figure 17. 4-wire μP I/F Timing
R/W
R/W
2
A4
A4
3
A3
A3
4
A2
A2
- 14 -
5
Hi-Z
Hi-Z
A1
A1
6
A0
A0
7
D7
D7
D7
8
D6
D6
D6
9
D5
D5
D5
10 11 12 13
D4
D4
D4
D3
D3
D3
D2
D2
D2
D1
D1
D1
14 15
D0
D0
D0
Hi-Z
2007/07

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