ak4116 AKM Semiconductor, Inc., ak4116 Datasheet - Page 17

• Manufacturer Part Number: ak4116
• Description: Low Power 48khz Digital Audio Receiver
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
There are eight events which cause the INT1-0 pins to go “H”.
INT1-0 pins output an OR’ed signal based on the above eight interrupt events. When masked, the interrupt event does not
affect the operation of the INT1-0 pins (the masks do not affect the resisters (UNLCK, PAR, etc.) themselves). Once
INT0 pin goes to “H”, it maintains “H” for 1024 cycles (this value can be changed by the EFH1-0 bits) after all events
not masked by mask bits are cleared. INT1 pin immediately goes to “L” when those events are cleared.
UNLCK, AUTO, V and AUDION bits indicate the interrupt status events above in real time. Once PAR, STC, QINT or
CINT bit goes to “1”, it stays “1” until the register is read. INT pin holds “H” for one sub-frame, then goes to “L” in this
case.
When the AK4116 loses lock, the channel status bits are initialized. In this initial state, INT0 outputs the OR’ed signal
between UNLCK and PAR bits. INT1 outputs the OR’ed signal to AUTO, V and AUDION. INT1-0 pins are “L” when
the PLL is OFF (Clock Operation Mode 1).
MS0156-E-03
Interrupt Handling
1. UNLCK: PLL unlock state detect
2. PAR:
3. AUTO:
4. V:
5. AUDION: Non-audio detection
6. STC:
7. QINT:
8. CINT:
Parity error or biphase coding error detection
Non-PCM or DTS-CD Bit Stream detection
Validity flag detection
Sampling frequency or pre-emphasis information change detection
U bit (Q-subcode) sync flag
Channel status sync flag
“1” when the PLL loses lock. The AK4116 loses lock when the distance between two preambles is
not correct or when those preambles are not correct.
“1” when parity error or biphase coding error is detected, updated every sub-frame cycle. Reading
this register resets it.
The OR function of NPCM and DTSCD bits is output to the AUTO bit.
“1” when validity flag is detected. Updated every sub-frame cycle.
“1” when the “AUDIO” bit in recovered channel status indicates “1”. Updated every block cycle.
“1” when FS3-0 or PEM bit changes. Reading this register resets it.
“1” when the Q-subcode differs from old one, and stays “1” until this register is read. Updated
every sync code cycle for Q-subcode. Reading this register resets it.
“1” when received C bits differ from old ones, and stays “1” until this register is read. Updated
every block cycle. Reading this register resets it.
UNLCK
1
0
0
Table 6. Interrupt handling
Event
PAR
x
1
0
- 17 -
Others
x
x
x
Previous Data
SDTO Pin
Output
“L”
[AK4116]
2005/08