ak7714 AKM Semiconductor, Inc., ak7714 Datasheet - Page 29

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ak7714

Manufacturer Part Number
ak7714
Description
20-bit Audio Codec With Dsp And Delay Ram
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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(6) Interface with microcomputer
Interface with the microcomputer is provided by 7 control signals: CS (Chip Select Bar), WRQ (Write ReQuest Bar),
SCLK (Serial data input CLocK), SI (Serial data Input), SO (Serial data Output), RDY (ReaDY) and DRDY (Data
ReaDY).
In the AK7714, two types of operations are provided; writing and reading during the reset phase (namely, system reset)
and those during the run phase. During the reset phase, data can be written to the control register, program
RAM,coefficient RAM, offset RAM, and external conditional jump code, and data can be read from the program
RAM,coefficient RAM and offset RAM. During the run phase, data can be written to the coefficient RAM,offset RAM and
external conditional jump code, and data on the DBUS (data bus) can be read from SO.
CS is used also for SO control in addition to the chip selection. When only one AK7714 is used without SO, CS = "L" is
allowed at all times.
If there is no communication with the microcomputer, set SCLK to "H" and SI to "L" for use.
Data is serially input and output with the MSB first. The following 8-bit command data is sent first, and the specified
work is performed.
M0018-E-00
Contents of command
Program RAM write
External conditional JMP code write [JCON]
Coefficient RAM write
Coefficient RAM write
Offset RAM write
Offset RAM write
CRAM/OFFRAM rewrite preparation[BNBW] during run phase:
Control register write
Program RAM read
Program CRAM read
Program OFRAM read
Command code list
NOTE: Do not send codes other than the above command codes.
Otherwise, an operation error may occur.
Conditions for use:
[RSCW] during reset phase:
[RSOW] during reset phase:
[RNOW] during run phase:
[RSPW] During reset phase:
[RNCW] during run phase:
[CONW] during reset phase:
- 29 -
both reset and run phases: Code (11000100)
during reset phase:
during reset phase:
during reset phase:
Code (C7C6C5C4C3C2C1C0)
Code (11000000)
Code (10001000)
Code (11000011)
Code (10010001)
Code (10100000)
Code (10100100)
Code (10010000)
Code (10010100)
Code (00000110)
Code (10100001)
[AK7714]
‘98/07

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