ak7742 ETC-unknow, ak7742 Datasheet - Page 12

• Manufacturer Part Number: ak7742
• Description: 24bit 2ch Adc + 24bit 4ch Dac With Audio Dsp
• Manufacturer: ETC-unknow

■
Note 28. It is necessity that the power is supplied and master clock is input when the IRESET pin goes to “H”.
■
1) SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT3
Note 29. BICK rising edge must not occur at the same time as LRCK edge.
Note 30. The serial data output is synchronized to BICK falling edge, and held until next BICK falling (spec -10ns) in
.
Rev.0.5b_PB
(Ta=-20ºC ~70ºC; AVDD=DVDD=3.0~3.6V, CL=20pF)
Slave mode
Master mode
Reset
Audio Interface
BICK frequency
BICK low level width
BICK high level width
Delay time from BICK “↑” to LRCK
Delay time from LRCK to BICK “↑”
Serial data input latch setup time
Serial data input latch hold time
Delay time from LRCK to serial data output
Delay time from BICK “↓” to serial data output (
BICK frequency
BICK duty cycle
Delay time from BICK “↑” to LRCK
Delay time from LRCK to BICK “↑”
Serial data input latch setup time
Serial data input latch hold time
Delay time from BICK “↓” to serial data output (
(Ta=-20ºC ~70ºC; AVDD=DVDD=3.0~3.6V)
IRESET
Slave mode. In case of the LRCK edge comes before BICK edge, data will be held until LRCK edge (spec
-10ns). In Master mode, serial data is held until 30ns before falling edge of BICK. Therefore, please use BICK
rising edge in both slave and master modes for a safety
Parameter
Parameter
(Note
28)
(Note
(Note
29)
29)
Symbol
tRST
Note 30
Note 30
-
12
)
)
-
fBCLK
tBCLKL
tBCLKH
tBLRD
tLRBD
tBSIDS
tBSIDH
tLRD
tBSOD
fBCLK
tBLRD
tLRBD
tBSIDS
tBSIDH
tBSOD
Symbol
latch.
min
600
min
150
150
-10
-10
-30
32
40
40
40
40
40
40
40
40
typ
typ
64
64
50
max
max
40
40
40
[AK7742]
2008/08
Unit
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
%
ns
ns
ns
ns
ns
fs
fs