ak4635ecb AKM Semiconductor, Inc., ak4635ecb Datasheet
ak4635ecb
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Mono CODEC with ALC & MIC/SPK/Video-AMP The AK4635 is a 16-bit mono CODEC with Microphone-Amplifier, Speaker-Amplifier and Video- Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Automatic Level Control) circuit. Output circuits include a Speaker-Amplifier and Mono Line ...
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PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz EXT Slave Mode / EXT Master Mode: ~ 7.35kHz 9. Output Master Clock Frequency: 256fs 10. Serial P Interface: ...
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... L Ordering Guide AK4635ECB 30 AKD4635 Evaluation board for AK4635 L Pin Layout 6 5 SDTO 4 BICK 3 FCK 2 PDN 1 VSAG Rev. 0.6 +85 C 29pin CSP (0.5mm pitch Top View I2C DVDD VSS2 VSS3 MCKO SPN SVDD SDTI MCKI AOUT CCLK/SCL CDTIO ...
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L Compatibility with AK4633 1. Function Function MIC-Amp Single End of Analog Input LPF Notch Filter ( Equalizer) SPK-Amp ALC Recovery Waiting Period Master Clock Mode PLL Mode Frequency BEEP Output Control Interface Video-Amp Package Rev. 0.6 AK4633 AK4635 0dB/+6dB/+10dB/+14dB ...
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No. Pin Name I/O Common Voltage Output Pin, 0.45 x AVDD D2 VCOM O Bias voltage of ADC inputs and DAC outputs. C1 VSS1 - Ground Pin D1 AVDD - Analog Power Supply Pin Output Pin for Loop Filter of ...
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L Handling of Unused Pin The unused I/O pins should be processed appropriately as below. Classification Pin Name MIC/MICP, LIN/MICN, MPI, AOUT, Analog SPP, SPN, VCOC, VIN, VOUT, VSAG MCKI, SDTI Digital CDTIO MCKO, SDTO (VSS1-3 =0V; Note 1) Parameter ...
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C; AVDD=DVDD=SVDD=3.3V; VSS1-3 =0V; fs=8kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 3.4kHz; EXT Slave Mode; unless otherwise specified) Parameter MIC Amplifier: MIC, LIN pins ; MDIF bit = “0”; (Single-ended input) Input Resistance Gain (MGAIN3-0 bits = “0000”) ...
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Parameter Speaker-Amp Characteristics: SDTI Output Voltage (0dBFS) S/(N+D) (Note 13) Output Noise Level (Note 13) Load Impedance (Note 14) Load Capacitance V Input Characteristics: Maximum Input Voltage (Note 17) Pull Down Current V Output Characteristics: Output Gain VIN = 100kHz ...
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AVDD(max)@MGAIN3-0 bits = “1001” When the signal larger than above value is input to MICP or MICN pin, ADC does not operate normally. Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.8 x AVDD (typ) Note ...
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VIN LPF CLAMP Figure 5. Load Capacitance C Note 21.PLL Master Mode (MCKI = 12MHz) and PMMP = PMADC = PMDAC = PMPFIL = PMSPK = PMVCM = PMPLL = MCKO = PMAO = M/S = “1” and PMV bit ...
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C; AVDD = 2.8 3.6V; DVDD = 1.6 Parameter ADC Digital Filter (Decimation LPF): Passband (Note 26) 0.16dB 0.66dB 1.1dB 6.9dB Stopband (Note 26) Passband Ripple Stopband Attenuation Group Delay (Note 27) Group Delay Distortion DAC ...
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C; AVDD = 2.8 3.6V, DVDD = 1.6 Parameter PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input: Frequency Pulse Width Low Pulse Width High MCKO Output: Frequency Duty Cycle except fs=29.4kHz, 32kHz ...
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Parameter PLL Slave Mode (PLL Reference Clock: FCK pin) FCK: Frequency DSP Mode: Pulse Width High Except DSP Mode: Duty Cycle BICK: Period Pulse Width Low Pulse Width High PLL Slave Mode (PLL Reference Clock: BICK pin) FCK: Frequency DSP ...
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Parameter EXT Slave Mode (Figure 15) MCKI Frequency: 256fs 512fs 1024fs Pulse Width Low Pulse Width High FCK Frequency (MCKI = 256fs) (MCKI = 512fs) (MCKI = 1024fs) Duty Cycle BICK Period BICK Pulse Width Low Pulse Width High Audio ...
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Parameter EXT Master Mode (Figure 6) MCKI Frequency: 256fs 512fs 1024fs Pulse Width Low Pulse Width High FCK Frequency (MCKI = 256fs) (MCKI = 512fs) (MCKI = 1024fs) Duty Cycle BICK: Period (BCKO1-0 bit = “00”) (BCKO1-0 bit = “01”) ...
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Parameter Control Interface Timing (3-wire Serial mode) CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “ ” to CCLK “ ” CCLK “ ” to CSN “ ” CCLK ...
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L Timing Diagram MCKI tCLKH FCK dFCK MCKO tMCKOH dMCK = tMCKOL x fMCK x 100% Figure 6. Clock Timing (PLL/EXT Master mode) (MCKO is not available at EXT Master Mode) FCK BICK (BCKP = "0") BICK (BCKP = "1") ...
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FCK BICK (BCKP = "1") BICK (BCKP = "0") SDTO SDTI Figure 8. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “1”) FCK tBFCK BICK SDTO SDTI Figure 9. Audio Interface Timing (PLL/EXT Master mode & Except ...
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FCK BICK (BCKP = "0") BICK (BCKP = "1") Figure 10. Clock Timing (PLL Slave mode; PLL Reference clock = FCK or BICK pin & DSP mode; MSBS = 0) FCK BICK (BCKP = "1") BICK (BCKP = "0") Figure ...
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MCKI tCLKH FCK tFCKH BICK tBCKH MCKO tMCKOH dMCK = tMCKOL x fMCK x 100% Figure 12. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode) Rev. 0.6 1/fCLK tCLKL 1/fFCK tFCKL tBCK tBCKL ...
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FCK BICK (BCKP = "0") BICK (BCKP = "1") SDTO SDTI Figure 13. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0) FCK tFCKB BICK (BCKP = "1") BICK (BCKP = "0") SDTO SDTI Figure 14. Audio ...
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MCKI tCLKH FCK tFCKH BICK tBCKH Figure 15. Clock Timing (EXT Slave mode) FCK tBFCK BICK tFSD SDTO SDTI Figure 16. Audio Interface Timing (PLL, EXT Slave mode & Except DSP mode) Rev. 0.6 1/fCLK tCLKL 1/fFCK tFCKL tBCK tBCKL ...
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CSN CCLK CDTI Figure 17. WRITE Command Input Timing CSN CCLK CDTI D2 Rev. 0.6 tCSS tCCKL tCCKH tCDS C1 C0 tCSH D1 D0 Figure 18. WRITE Data Input Timing - 23 - [AK4635] VIH VIL VIH VIL tCCK tCDH ...
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CSN CCLK CDTI D3 SDA tBUF tLOW tR SCL tHD:STA Stop Start PMADC bit SDTO PDN Rev. 0.6 tDCD D2 D1 Figure 19. Read Data Output Timing tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 20 Bus Mode ...
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L System Clock There are the following five clock modes to interface with external devices. Mode PLL Master Mode PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 (PLL Reference Clock: FCK or BICK pin) EXT ...
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L Master Mode/Slave Mode The M/S bit selects either master or slave modes. M/S bit = “1” selects master mode and “0” selects slave mode. When the AK4635 is power-down mode (PDN pin = “L”) and exits reset state, the ...
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When PLL2 bit is “0” (PLL reference clock input is FCK or BICK pin), the sampling frequency is selected by FS3-2 bits. (Table 6) FS3 bit FS2 bit Mode Others Table ...
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L PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”) When an external clock (12MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the MCKO, BICK and FCK clocks are generated by an internal PLL circuit. ...
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L PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, BICK or FCK pin. The required clock to the AK4635 is generated by an ...
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PLL reference clock: BICK or LRCK pin Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits. AK4635 Figure 25 PLL Slave Mode 2 (PLL Reference Clock: BICK pin) AK4635 Figure 26. PLL Slave Mode 2 (PLL Reference ...
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L EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) When PMPLL bit is “0”, the AK4635 becomes EXT Slave mode. Master clock is input from the MCKI pin, the internal PLL circuit is not operated. This mode ...
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L EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) The AK4635 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the MCKI pin, the internal PLL ...
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L Audio Interface Format Four types of data formats are available and are selected by setting the DIF1-0 bits. is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. FCK and BICK ...
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FCK ...
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L System Reset When power-up, the PDN pin should be “L” and change to “H” after all power are supplied. “L” time of 150ns or more is needed to reset in the AK4635. The ADC enters an initialization cycle when ...
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MPI pin 1k MICP pin MICNpin 1k L MIC Gain Amplifier The AK4635 has a Gain Amplifier for Microphone input. These gains are selected by the MGAIN3-0 bit. The typical input impedance is 30k . MGAIN3 bit MGAIN2 bit 0 ...
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L Digital Block The digital block consists of block diagram as shown in a recording path or a playback path by setting ADCPF bit, PFDAC bit and PFSDO bit. PMADC bit HPFAD bit (1) ADC: Include the Digital Filter (LPF) ...
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Mode Recording Mode Reproduction Mode Loop Back Mode ADC DAC Figure 40. Path at Recording Mode (default) 1st Order ADC HPF DAC SMUTE ADC DAC Figure 42. Path at Recording & Playback Mode Rev. 0.6 ADCPF bit PFDAC bit PFSDO ...
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L Digital Programmable Filter Circuit st The AK4635 has 2 steps of 1 order HPF, 1 path. (1) High Pass Filter (HPF) Normally, this HPF is used as a Wind-Noise Reduction Filter. This is composed with 2 steps of 1st ...
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Equalizer This block can be used as Equalizer or Notch Filter. ON/OFF 5-band Equalizer (EQ1, EQ2, EQ3, EQ4 and EQ5) can be controlled independently by EQ1, EQ2, EQ3, EQ4 and EQ5 bits. When Equalizer is OFF, the audio ...
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L Input Digital Volume (Manual Mode) When ADCPF bit = “1” and ALC1 bit = “0”, ALC block becomes an input digital volume (manual mode). The digital volume’s gain is set by IVOL7-0 bits as shown in out. The zero ...
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L Output Digital volume (Manual mode) When ADCPF bit = “0” and ALC2 bit = “0”, ALC block become an output digital volume (manual mode). The digital volume’s gain is set by OVOL7-0 bits as shown in at zero cross ...
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L ALC Operation ALC Operation works in ALC block. When ADCPF bit = “1”, ALC operation is enable for recording path. When ADCPF bit = “0”, ALC operation is enable for playback path. The ON/OFF of ALC operation for recording ...
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ALC Recovery Operation The ALC recovery operation waits for the WTM2-0 bits If the input signal does not exceed “ALC recovery waiting counter reset level” recovery operation is executed. The VOL value is automatically incremented by RGAIN1-0 bits reference ...
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IREF7-0bits F1H F0H EFH : C5H : 92H 91H 90H : Table 30. Reference Level at ALC Recovery operation for recoding OREF5-0bits 3CH 3BH 3AH : 28H : 25H 24H 23H : Table 31. ...
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The Volume at the ALC Operation The current volume value at the ALC operation is reflected by VOL7-0 bits enable to check the current volume value by reading the register value of VOL7-0 bits. This function is ...
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Example of ALC for Playback Operation Table 35 shows the example of the ALC setting for playback. Register Name Comment LMTH1-0 Limiter detection Level ZELM Limiter zero crossing detection ZTM1-0 Zero crossing timeout period Recovery waiting period WTM2-0 *WTM1-0 ...
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The following registers must not be changed during the ALC operation. These bits should be changed, after the ALC operation is finished by ALC1 bit = ALC2 bit = “0” or PMPFIL bit = “0”. After ALC1 bit and ALC2 ...
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L SOFTMUTE Soft mute operation is performed in the digital input domain. When the SMUTE bit changes to “1”, the input signal is attenuated by (“0”) during the cycle of 245/fs (31msec@fs=8kHz). When the SMUTE bit is returned to “0”, ...
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L MONO LINE OUTPUT (AOUT pin) A signal of DAC is output from the AOUT pin. When the DACA bit is “0”, this output is OFF. When the LOVL bit is “1”, this gain changes to +2dB. The load resistance ...
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L Speaker Output AK4635 has a Mono Class-D Speaker-Amp. Power supply for Speaker-Amp(SVDD) can be set from 2. 4.0V. The Speaker is mono and BTL output, and can drive dynamic speaker and piezo speaker without LPF (filter-less). This ...
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Piezo Speaker> When a piezo speaker is used, resistances more than 10 should be connected between the SPP/SPN pins and speaker in series, respectively, as shown in Figure Figure 48, in order to protect SPK-Amp of the ...
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L BEEP Generate The AK4635 generates and output square wave from speaker amp. After outputting the signal during the time set by BPON6-0 bits, the AK4635 stops the output signal during the time set by BPOFF6-0 bits set by BPTM6-0 ...
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BPFR1-0 bit Note 40. Sampling frequency is 8kHz, 16kHz, 32kHz or 48kHz. Note 41. Sampling frequency is 11.025kHz, 22.05kHz or 44.1kHz. Table 38. Beep signal frequency (PLL Master/Slave Mode: reference clock: MCKI) (N/A: Not available) BPFR1-0 ...
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OFF Time of BEEP Generator [msec] BPOFF7-0 bit fs = 48kHz system (Note 0H 8.0 1H 16.0 2H 24.0 3H 32 FDH 2032 FEH 2040 FFH 2048 Note 40. Sampling frequency is 8kHz, 16kHz, 32kHz or ...
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L Video Block Video-Amp has a drivability for a load resistance of 150 . The AK4635 has a composite input and output. A Low Pass Filter (LPF) and Gain Control Amp (GCA) are integrated and both DC output and Sag ...
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SAGC bit 0 1 VSAG2 bit VSAG1 bit 0 1 Others Table 46. Sag Compensation circuit setting (SACG bit = “1”) (N/A: Not available) VGCA4-0 bits 17H 16H 15H : 04H 03H 02H 01H 00H Rev. 0.6 Output Method DC ...
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L Serial Control Interface (1) 3-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written and read by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this interface consists of Read/Write, Register ...
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I C-bus Control Mode (I2C pin = “H”) 2 The AK4635 supports the fast-mode I to (DVDD+0.3)V or less voltage. (2)-1. WRITE Operations Figure 54 shows the data transfer sequence for the I HIGH to LOW transition on ...
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READ Operations Set the R/W bit = “1” for READ operation of the AK4635. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt ...
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SDA SCL S start condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION SDA SCL Rev. 0.6 Figure 60. START and STOP Conditions Figure 61. Acknowledge on the I C-Bus data ...
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L Register Map Addr Register Name D7 00H Power Management 1 PMPFIL 01H Power Management 2 PMV 02H Signal Select 1 SPOUTE 03H Signal Select 2 PFSDO 04H Mode Control 1 PLL3 05H Mode Control 2 ADRST 06H Timer Select ...
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Addr Register Name 30H Digital Filter Select 2 31H Reserved 32H E1 Co-efficient 0 E1A7 33H E1 Co-efficient 1 E1A15 34H E1 Co-efficient 2 E1B7 35H E1 Co-efficient 3 E1B15 36H E1 Co-efficient 4 E1C7 37H E1 Co-efficient 5 E1C15 ...
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L Register Definitions Addr Register Name D7 00H Power Management 1 PMPFIL R/W R/W Default 0 PMADC: ADC Block Power Control 0: Power down (default) 1: Power up When the PMADC bit changes from “0” to “1”, the initialization cycle ...
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Addr Register Name D7 01H Power Management 2 PMV R/W R/W Default 0 PMPLL: PLL Block Power Control Select 0: PLL is Power down and External is selected. (default) 1: PLL is Power up and PLL Mode is selected. MCKO: ...
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Addr Register Name 03H Signal Select 2 PFSDO R/W R/W Default ADCPF: Select of Input signal to Programmable Filter/ALC. 0: SDTI 1: Output of ADC (default) PFDAC: Select of Input signal to DAC. 0: SDTI (default) 1: Output of Programmable ...
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Addr Register Name 05H Mode Control 2 ADRST R/W Default FS3-0: Setting of Sampling Frequency These bits are selected to sampling frequency at PLL mode and MCKI frequency at EXT mode. Default: “0000” BCKP, MSBS: “00” (default) (Table FCKO: Select ...
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Addr Register Name 07H ALC Mode Control 1 LFST R/W R/W Default LMTH1-0: ALC Limiter Detection Level / Recovery Waiting Counter Reset Level LMTH1 bit is located at D6 bit of 0BH. Default: “01” RGAIN1-0: ALC Recovery GAIN Step RGAIN1 ...
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Addr Register Name 09H Input Digital Volume Control IVOL7 R/W Default IVOL7-0: Input Digital Volume; 0.375dB step, 242 Level Default: “91H” (0.0dB) Addr Register Name 0AH Digital Volume Control OVOL7 R/W Default OVOL7-0: Output Digital Volume; 0.375dB step, 242 Level ...
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Addr Register Name 0EH Mode Control 3 DATT1 R/W Default READ: Read function Enable 0: Disable (default) 1: Enable VSAG2-0: Select common level of Video-amp at Sag Compensation mode (SAGC = “1”). Default: “101” MDIF: Single-ended / Full-differential Input Select ...
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Addr Register Name 11H Digital Filter Select 1 R/W Default HPFAD: HPF Enable in ADC block 0: Disable 1: Enable (default) When HPFAD bit is “0”, HPFAD block is bypassed (0dB). When HPFAD bit is “1”, F1A13-0, F1B13-0 bits are ...
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Addr Register Name 21H BEEP ON Time BPON7 R/W Default BPON7-0: Setting ON-time of BEEP signal output Default: “00H” Addr Register Name 22H BEEP OFF Time BPOFF7 R/W R/W Default BPOFF7-0: Setting OFF-time of BEEP signal output Default: “00H” Addr ...
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Addr Register Name 2CH LPF Co-efficient 0 2DH LPF Co-efficient 1 2EH LPF Co-efficient 2 2FH LPF Co-efficient 3 R/W Default F2A13-0, F2B13-0: LPF Coefficient (14bit x 2) Default: “0000H” Addr Register Name 30H Digital Filter Select 2 R/W Default ...
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Addr Register Name 32H E1 Co-efficient 0 33H E1 Co-efficient 1 E1A15 34H E1 Co-efficient 2 35H E1 Co-efficient 3 E1B15 36H E1 Co-efficient 4 37H E1 Co-efficient 5 E1C15 38H E2 Co-efficient 0 39H E2 Co-efficient 1 E2A15 3AH ...
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Figure 63 and Figure 64 show the system connection diagram. The evaluation board [AKD4635] demonstrates the optimum layout, power supply arrangements and measurement results. < MIC Single-end Input > DSP & µ ...
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MIC differential Input > DSP & µ ...
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Grounding and Power Supply Decoupling The AK4635 requires careful attention to power supply and grounding arrangements. AVDD, DVDD and SVDD are usually supplied from the system’s analog supply. If AVDD, DVDD and SVDD are supplied separately, the correct power ...
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WL-CSP: 2.5mm x 3.0mm Top View 2.5 0 4635 4 XXXX Rev. 0.6 PACKAGE Bottom View 3.0 0 0.3 S ...
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These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status ...