ak4628 AKM Semiconductor, Inc., ak4628 Datasheet - Page 30

ak4628

Manufacturer Part Number

ak4628

Description

High Performance Multi Channel Audio Codec

Manufacturer

AKM Semiconductor, Inc.

Datasheet

1.AK4628.pdf (41 pages)

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ASAHI KASEI

MS0211-E-02

(2) I

AK4628 supports the standard-mode I

system (max:400kHz). The CSN pin should be connected to DVDD at the I

Figure 17 shows the data transfer sequence at the I

A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 22). After the

START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data

direction bit (R/W) (Figure 19). The most significant five bits of the slave address are fixed as “00100”. The next

two bits are CAD1 and CAD0 (device address bits). These two bits identify the specific device on the bus. The

hard-wired input pins (CAD1 pin and CAD0 pin) set them. If the slave address match that of the AK4628 and R/W

bit is “0”, the AK4628 generates the acknowledge and the write operation is executed. If R/W bit is “1”, the AK4628

generates the not acknowledge since the AK4628 can be only a slave-receiver. The master must generate the

acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse (Figure 23).

The second byte consists of the address for control registers of the AK4628. The format is MSB first, and those most

significant 3-bits are fixed to zeros (Figure 20). Those data after the second byte contain control data. The format is

MSB first, 8bits (Figure 21). The AK4628 generates an acknowledge after each byte has been received. A data

transfer is always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA

line while SCL is HIGH defines a STOP condition (Figure 22).

The AK4628 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the

AK4628 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte

instead of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal

5bits address counter is incremented by one, and the next data is taken into next address automatically. If the address

exceed 1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data

will be overwritten.

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data

line can only change when the clock signal on the SCL line is LOW (Figure 24) except for the START and the STOP

condition.

C-bus Control Mode (I2C= “H”)

SDA

Slave

Address

Figure 18. Data transfer sequence at the I

(Those CAD1/0 should match with CAD1/0 pins)

Figure 21. Byte structure after the second byte

R/W

Sub

Address(n)

C-bus (max:100kHz). Then AK4628 does not support a fast-mode I

Figure 20. The second byte

Figure 19. The first byte

(*: Don’t care)

C-bus mode. All commands are preceded by a START condition.

- 30 -

Data(n)

Data(n+1)

CAD1

C-bus mode

C-bus mode.

CAD0

x x x x x x x x x x x x

Data(n+x)

R/W

[AK4628]

2004/03

C-bus

ak4628 AKM Semiconductor, Inc., ak4628 Datasheet - Page 30

ak4628

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