ak4589 AKM Semiconductor, Inc., ak4589 Datasheet - Page 40

• Manufacturer Part Number: ak4589
• Description: 2/8-channel Audio Codec With Dir
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0339-E-00
Addr Register Name
01H
DFS1-0: Sampling speed mode (see Table 1)
CKS0-1: Master clock frequency select (see Table 2)
SDOS: SDTO1 source select
LOOP1-0: Loopback mode enable
ACKS: Master Clock Frequency Auto Setting Mode Enable
Control 2
0: ADC
1: DAUX
00: Normal (No loop back)
01: LIN → LOUT1, LOUT2, LOUT3, LOUT4
10: SDTI1(L) → SDTI2(L), SDTI3(L), SDTI4(L)
11: N/A
ADC is selected.
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically at ACKS bit “1”. In this case, the setting of DFS1-0
bits are ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode.
The setting of DFS1-0 bits are ignored at ACKS bit “1”.
SDOS bit should be set to “0” at TDM bit “1”.
In the case of PWADN bit =”0” and PWDAN bit =”0”, the setting of SDOS bit becomes invalid. And
The output of SDTO1 becomes “L” at PWADN bit =”0”.
Default
In this mode the input DAC data to SDTI2-4 is ignored.
RIN → ROUT1, ROUT2, ROUT3, ROUT4
The digital ADC output (DAUX1 input if SDOS = “1”) is connected to the digital DAC input. In
this mode, the input DAC data to SDTI1-3 is ignored. The audio format of SDTO1 at loopback
mode becomes mode 2 at mode 0, and mode 3 at mode 1, respectively.
SDTI1(R) → SDTI2(R), SDTI3(R), SDTI4(R)
LOOP1-0 bits should be set to “00” at TDM bit “1”.
In the case of PWADN bit =”0” and PWDAN bit =”0”, the setting of LOOP1-0 bits become
invalid. And ADC is selected. And it becomes the normal operation (No loop back).
CKS1
D7
0
DFS1
D6
0
- 40 -
LOOP1
D5
0
LOOP0
D4
0
SDOS
D3
0
DFS0
D2
0
ACKS
D1
0
[AK4589]
2004/09
CKS0
D0
0