ak4537 AKM Semiconductor, Inc., ak4537 Datasheet - Page 54

• Manufacturer Part Number: ak4537
• Description: 16-bit 6 Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0202-E-04
Addr
09H
LMTH:
RATT:
LMAT1-0:
ZELM:
0: Enable (Default)
1: Disable
LMTH
Register Name
ALC Mode Control 1
0
1
The ALC1 limiter detection level and the ALC1 recovery counter reset level may be offset by about 2dB.
Default is “0”.
During the ALC1 recovery operation, the number of steps changed from the current IPGA value is set. For
example, when the current IPGA value is 30H and RATT bit = “1” is set, the IPGA changes to 32H by the
ALC1 recovery operation and the output signal level is gained up by 1dB (=0.5dB x 2). When the IPGA value
exceeds the reference level (REF6-0 bits), the IPGA value does not increase.
During the ALC1 limiter operation, when either Lch or Rch exceeds the ALC1 limiter detection level set by
LMTH, the number of steps attenuated from the current IPGA value is set. For example, when the current
IPGA value is 47H and the LMAT1-0 bits = “11”, the IPGA transition to 43H when the ALC1 limiter
operation starts, resulting in the input signal level being attenuated by 2dB (=0.5dB x 4). When the attenuation
value exceeds IPGA = “00” ( 8dB), it clips to “00”.
When the ZELM bit = “0”, the IPGA of each L/R channel perform a zero crossing or timeout independently
and the IPGA value is changed by the ALC1 operation. The zero crossing timeout is the same as the ALC1
recovery operation. When the ZELM bit = “1”, the IPGA value is changed immediately.
Default
ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 28)
ALC1 Recovery GAIN Step (see Table 29)
Enable zero crossing detection at ALC1 Limiter operation
R/W
ALC1 Limiter ATT Step (see Table 30)
Table 28. ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level
ALC1 Limiter Detection Level
ADC Input
ADC Input
LMAT1
Table 29. ALC1 Recovery Gain Step Setting
0
0
1
1
6.0dBFS
4.0dBFS
Table 30. ALC1 Limiter ATT Step Setting
RD
D7
0
0
RATT
0
1
LMAT0
ALC2
R/W
0
1
0
1
D6
1
GAIN STEP
ALC1 Recovery Waiting Counter Reset Level
- 54 -
ALC1
1
2
R/W
ATT STEP
6.0dBFS
4.0dBFS
D5
0
1
2
3
4
ZELM
R/W
D4
0
ADC Input
ADC Input
Default
Default
LMAT1
R/W
D3
0
8.0dBFS
6.0dBFS
LMAT0
R/W
D2
0
RATT
R/W
D1
0
Default
[AK4537]
LMTH
2005/04
R/W
D0
0