ak4538 AKM Semiconductor, Inc., ak4538 Datasheet
ak4538
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ak4538 Summary of contents
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... The AK4538 targeted at PDA and other low-power, small size applications. It features a 16-bit stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4538 is available in a 52-QFN, utilizing less board space than competitive offerings. ...
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Audio Interface Format : MSB First, 2’s compliment 2 ADC : I S, 16bit MSB justified 2 DAC : I S, 16bit MSB justified, 16bit LSB justified 11 - 12. Power Supply: 13. Power Supply ...
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... ASAHI KASEI n Ordering Guide AK4538VN AKD4538 Evaluation board for AK4538 n Pin Layout (52pin QFN MICOUT 1 MDT 2 EXT 3 MPE 4 MPI 5 INT 6 VCOM 7 AVSS 8 AVDD 9 PVDD 10 PVSS 11 VCOC MS0198-E-01 10 +70 C 52pin QFN (0.4mm pitch) AK4538VN ...
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No. Pin Name I/O 1 MICOUT O Microphone Analog Output Pin 2 MDT I Microphone Detect Pin (Internal pull down by 500k ) 3 EXT I External Microphone Input Pin (Mono Input) 4 MPE O MIC Power Supply Pin for ...
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... BEEPL I Lch Stereo Beep Signal Input Pin 51 AIN I Analog Input Pin Connect. No internal bonding. Note: All input pins except analog input pins (INT, EXT, AIN, MIN, AUXIN+, AUXIN-, BEEPM, BEEPL, and BEEPR) should not be left floating. MS0198-E-01 Function - 5 - [AK4538] 2003/5 ...
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... AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0198-E-01 ABSOLUTE MAXIMUM RATINGS Symbol min AVDD DVDD PVDD HVDD (Note 2) GND1 (Note 2) GND2 (Note 2) GND3 IIN VINA VIND Ta Tstg Symbol min AVDD 2.4 DVDD 2.4 PVDD 2.4 HVDD 2 [AK4538] max Units 0.3 4.6 V 0.3 4.6 V 0.3 4.6 V 0 0.3 AVDD+0.3 V 0.3 DVDD+0 ...
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... ANALOG CHARACTERISTICS min 2.22 2.47 - 0.165 250 5 0.1 8 0.168 0.198 =10k , DAC LOUT/ROUT L 1.94 1. =20k , DAC MOUT+/MOUT 0.31 3.56 3. [AK4538] typ max Units 2. 1.25 mA 0.247 mV 750 500 0.5 0.9 dB +27.5 dB IPGA ADC 16 Bits 0.228 Vpp ...
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... HP-Amp MS0198-E-01 min =22.8 , DAC HPL/HPR, DATT=0dB L 1. MOUT2 MIN 2. MOUT2 10 HPL/HPR pin 47 F > 6 Figure 2. Headphone-amp output circuit - 8 - [AK4538] typ max Units 1.92 2.30 Vpp 70 dBFS 0.1 0 300 pF SPP/SPN, ALC2=OFF 2.96 3.55 Vpp 1.98 Vpp ...
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... Note 19. PMMIC=PMADC=PMDAC=PMMO=PMHPL=PMHPR=PMVCM=PMPLL=PMXTL=PMBPM =PMBPS=PMLO=PMAUX= “1”, PMSPK= “0”. Note 20. PMMIC=PMADC=PMDAC=PMMO=PMSPK=PMVCM=PMPLL=PMXTL=PMBPM=PMBPS=PMLO =PMAUX= “1”, PMHPL=PMHPR= “0”. Note 21. All digital input pins are fixed to DVDD or DVSS. MS0198-E-01 min typ 17 1.2 6 [AK4538] max Units 100 A 100 A 100 ...
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... Note 24. These frequency responses scale with fs high-level and low frequency signal is input, the analog output clips to the full-scale. MS0198-E-01 FILTER CHARACTERISTICS Symbol min 27 24 [AK4538] typ max Units 17.4 kHz 20.0 - kHz 21.1 - kHz kHz 0 17 20.0 kHz 22.05 - kHz kHz 0. 16.8 1/fs 0 ...
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C; AVDD, DVDD, PVDD, HVDD=2.4 Parameter High-Level Input Voltage Low-Level Input Voltage Input Voltage at AC Coupling High-Level Output Voltage (Iout= 200 A) Low-Level Output Voltage (Except SDA pin: Iout=200 A) ( SDA pin: Iout= 3mA) Input ...
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... PMADC “ ” to SDTO valid (Note 31) Note 29. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 30. The AK4538 can be reset by the PDN pin = “L”. Note 31. This is the count of LRCK “ ” from the PMADC bit = “1”. Purchase of Asahi Kasei Microsystems Co., Ltd I patent to use the components in the I defined by Philips ...
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... LRCK BICK tBCKH MCKO dMCK 1000pF MCKI Input MS0198-E-01 1/fCLK tCLKL 1/fs tBCK tBCKL fMCK dMCK Figure 3. Clock Timing Measurement Point 100k AGND AGND Figure 4. MCKI AC Coupling Timing - 13 - [AK4538] VIH VIL VIH VIL VIH VIL 50%DVDD 1/fCLK tACW tACW VAC 2003/5 ...
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LRCK tBLR BICK tLRS SDTO SDTI Figure 5. Audio Interface Timing (Slave mode) LRCK tMBLR BICK SDTO SDTI Figure 6. Audio Interface Timing (Master mode) MS0198-E-01 tLRB tBSD tSDS tSDH dBCK tBSD tSDS tSDH - 14 - VIH VIL VIH ...
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... CCLK CDTI CDTO Figure 7. WRITE/READ Command Input Timing CSN CCLK CDTI D2 CDTO MS0198-E-01 tCSS tCCKL tCCKH tCDS tCDH C1 C0 Hi-Z tCSH D1 D0 Hi-Z Figure 8. WRITE Data Input Timing - 15 - [AK4538] VIH VIL VIH VIL VIH R/W VIL tCSW VIH VIL VIH VIL VIH VIL 2003/5 ...
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... CSN CCLK CDTI A1 Hi-Z CDTO CSN CCLK CDTI CDTO D2 MS0198-E-01 A0 tDCD D7 Figure 9. READ Data Output Timing 1 tCSW tCSH D1 D0 Figure 10. READ Data Output Timing [AK4538] VIH VIL VIH VIL VIH VIL D6 50%DVDD VIH VIL VIH VIL VIH VIL tCCZ Hi-Z 50%DVDD 2003/5 ...
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... SCL tHD:STA Stop Start CSN SDTO PDN MS0198-E-01 tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 11 Bus Mode Timing tPDV tPD Figure 12. Power Down & Reset Timing - 17 - [AK4538] VIH VIL tSP VIH VIL tSU:STO Stop VIH VIL 50%DVDD VIL 2003/5 ...
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... ASAHI KASEI n Master Clock Source The AK4538 requires a master clock (MCLK). This master clock is input to the AK4538 by connecting a X’tal oscillator to XTI and XTO pins or by inputting an external CMOS-level clock to the XTI pin or by inputting an external clock that is greater than 50% of the DVDD level to the XTI pin through a capacitor. ...
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... AC Coupling Input XTI C External Clock XTO Figure 15. External Clock mode (Input : 50%DVDD) - Note: This clock level must not exceed DVDD level 0.1 F) MS0198-E-01 MCKPD = "0" 25k PMXTL = "0" AK4538 MCKPD = "0" 25k PMXTL = "1" AK4538 - 19 - [AK4538] 2003/5 ...
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... The phase between these clocks does not matter. LRCK and BICK must be present whenever the AK4538 is operating (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided, the AK4538 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4538 in power-down mode (PMADC bit = PMDAC bit = “ ...
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... LRCK and BICK are output from the AK4538 in master mode. The clock to the MCKI pin must not stop during normal operation (PMPLL bit = “1”). If this clock is not provided, the AK4538 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK4538 in power-down mode (PMADC bit = PMDAC bit = “ ...
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... The M/S pin selects either master or slave modes. M/S pin = “H” selects master mode and “L” selects slave mode. The AK4538 outputs MCKO, BICK and LRCK in master mode. The AK4538 outputs only MCKO in slave mode, while BICK and LRCK must be input separately. ...
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... All data formats can be used in both master and slave modes. LRCK and BICK are output from AK4538 in master mode, but must be input to AK4538 in slave mode. If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit 16bit data is converted 8-bit data. And when the DAC playbacks this 8-bit data 8-bit data will be converted to 256 at 16-bit data and this is a large offset ...
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LRCK BICK(32fs) SDTO( SDTI( BICK(64fs SDTO(o) SDTI( 15:MSB, 0:LSB LRCK BICK(32fs SDTO( ...
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... ASAHI KASEI n MIC Input “MGAIN” Mic In 0dB/+20dB The AK4538 has the following functions for Mic Input. st (1) 1 MIC Amplifier of 20dB gain that can be selected on/off by “MGAIN” bit. nd (2) 2 Amplifier that has PGA with ALC. This volume is controlled by “IPGA6-0” bit as Table 14. ...
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... ASAHI KASEI n MIC Gain Amplifier AK4538 has a Gain Amplifier for Microphone input. This gain is 0dB or +20dB, selected by the MGAIN bit. The typical input impedance is 30k . n MIC Power The MPI and MPE pins supply power for the Microphone. These output voltages are 0.75 x AVDD (typ) and the maximum output current is 1 ...
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... IPGA value is attenuated at the zero-detect points of the waveform. [2] ALC1 Recovery Operation The ALC1 recovery refers to the amount of time that the AK4538 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC1 recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC1 limiter operation. If the input signal does not exceed the “ ...
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... Enable Table 18. Example of the ALC1 setting Example: * The value of IPGA should be the same or smaller than REF’ [AK4538] fs=16kHz fs=44.1kHz Data Operation Data Operation 1 -4dBFS 1 -4dBFS 00 Don’t use 00 Don’t use 0 ...
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... ASAHI KASEI n De-emphasis Filter The AK4538 includes the digital de-emphasis filter (tc = 50/ IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter. DEM1 Bass Boost Function The BST1-0 bits control the amount of low frequency boost applied to the DAC output signal. If the BST1-0 bits are set to “ ...
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... ASAHI KASEI n Digital Attenuator The AK4538 has a channel-independent digital attenuator (256 levels, 0.5dB step, Mute). The attenuation level of each channel can be set by the ATTL/R7-0 bits (Table 21). When the DATTC bit = “1”, the ATTL7-0 bits control both Lch and Rch attenuation levels. When the DATTC bit = “0”, the ATTL7-0 bits control Lch level and ATTR7-0 bits control Rch level ...
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... ASAHI KASEI n AUX Input AUXIN+ AUXIN- AUX input is differential input. The AK4538 has a volume for AUX Input. This Volume is controlled by GN3-0 bits as shown in Table 22.The AK4538 register control for GN3-0 does not offer any de-clicking function at volume setting change. MS0198-E-01 “GN3-0” ...
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... The signal from the BEEPM pin is mixed to the Headphone-amp through a –20dB gain stage. The signal from the BEEPM pin is mixed to the Speaker-amp without gain. The internal feedback resistance is 20k Ri BEEPL Ri BEEPR Ri BEEPM MS0198-E- 20k BPMHP Rf = 20k Rf = 20k 1/2 1/2 AK4538 Figure 25. Block Diagram of BEEP pins - 32 - [AK4538] 30% . BPSHP HPL MIX -20dB HPR MIX BPSHP BPSSP SPK MIX BPMSP 2003/5 ...
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... C when the capacitor value on MUTET pin when the capacitor value on HPL(HPR) pin is “C”. f that the common voltage goes to GND Headphone 16 0. [Hz] fc [Hz] BOOST=MID 2.7V 152.5 63 10.0 105.8 43 4.8 71.2 27 10.0 49.7 20 4.8 Table 23. External Circuit Example - 33 - [AK4538] = 188ms Output Power [mW] 3.0V 3.3V 12.4 15.0 6.0 7.2 12.4 15.0 6.0 7.2 2003/5 ...
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... When the SPPS bit is “0”, the Speaker-amp enters power-save-mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin goes to HVDD/2 voltage. And then the Speaker output gradually changes to the HVDD/2 voltage and this mode can reduce pop noise at power-up. When the AK4538 is powered down, pop noise can be also reduced by first entering power-save-mode. ...
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... The mixed Lch/Rch signal of DAC is output from the MOUT2 pin. When the MOUT2 bit is “0”, this output is OFF and the MOUT2 pin is forced to VCOM voltage. The load impedance is 10k (min.). When the PMSPK bit is “0”, the Speaker-amp enters power-down-mode and the output is placed in a Hi-Z state. MS0198-E-01 20k 30% BPSSP 45%AVDD 20k 30% BPSSP 45%AVDD BEEPL BEEPR - 35 - [AK4538] SPK-Amp SPP SPN 2003/5 ...
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... FS-3.9dB = -7.2dBV +16.1dB -8dB -23.3dBV ALC2 ATT+DAC SPK-AMP - 36 - [AK4538] ALC2 Recovery operation 7.2dBV 2048/fs=46.4ms (at 44.1kHz) 512/fs=46.4ms (at 11.025kHz) Yes (Timeout = Period Time) 1dB step Full-differential 0.4dBV 0dBV -1.6dBV Single-ended -5.6dBV -10dBV -20dBV -30dBV ...
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... Amp for mono output has 6dB gain and -17dB gain that are set by the MOGN bit. MS0198-E-01 ATT IPGA “MICL” “DAHS” ATT+DAC Stereo Line Out “AUXL” Volume Figure 32. Stereo Line Output IPGA “MICM” “DAMO” “MOGN” 1/2 1/2 -17dB/6dB Figure 33. Mono Output - 37 - [AK4538] MOUT+ MOUT- 2003/5 ...
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... Chip Address (C1="1", C0=CAD0) R/W : READ / WRITE ("1" : WRITE, "0" : READ Register Address Control Data MS0198- Figure 34. Serial Control I/F Timing - 38 - [AK4538 Hi 2003/5 ...
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... A “0” indicates that the write operation executed. The second byte consists of the control register address of the AK4538. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 37). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 38) ...
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... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4538. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. ...
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SDA SCL S start condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION SDA SCL MS0198-E-01 Figure 41. START and STOP Conditions Figure 42. Acknowledge on the I C-Bus data line ...
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Register Map n Addr Register Name D7 00H Power Management 1 PMVCM 01H Power Management 2 MCKPD 02H Signal Select 1 MOGN 03H Signal Select 2 DAHS 04H Mode Control 1 PLL1 05H Mode Control 2 FS2 06H DAC Control ...
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... MCLK, BICK and LRCK must always be present unless PMMIC=PMADC=PMDAC=PMSPK= “0” or PDN pin = “L”. The paths from BEEP to HP-Amp and SPK-Amp can operate without these clocks. MS0198-E- PMBPS PMBPM PMLO PMMO R/W R/W R/W R [AK4538 PMAUX PMMIC PMADC R/W R/W R 2003/5 ...
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Addr Register Name D7 01H Power Management 2 MCKPD R/W R/W Default PMDAC: DAC Block Power Control 0: Power down (Default) 1: Power up PMHPR: Rch of Headphone-Amp Power Control 0: Power down (Default) 1: Power up PMHPL: Lch of ...
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... When the PSMO bit = “0”, Mono Line Output is in power save mode and the MOUT+ and MOUT- pins output 0.45 x AVDD voltage. MOGN: Gain control for mono output 0: +6dB (Default) 1: -17dB MS0198-E- PSMO DAMO MICM R/W R/W R/W R [AK4538 BPSSP BPMSP ALCS MOUT2 R/W R/W R/W R 2003/5 ...
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... OFF (Default MS0198-E-01 ATT IPGA “MICL” “DAHS” ALC2 “AUXL” “BPMSP” “BPSSP” Figure 44. Speaker-amp switch control PSLO AUXL MICL R/W R/W R/W R [AK4538] “ALCS” SPK-AMP 1/2 1 BPSHP BPMHP HPL HPR R/W R/W R/W R 2003/5 ...
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... DAC signal is mixed to Headphone-amp and MOUT2 at the DAHS bit = “1”. MIC IN 0dB/+20dB ATT+DAC AUXIN+ AUXIN- Volume BEEPM IN BEEPL IN BEEPR IN MS0198-E-01 “MICL” ATT IPGA “DAHS” “AUXL” “BPMHP” “BPSHP” Figure 45. Headphone-amp switch control - 47 - [AK4538] HPL HPL MUTE HPR HPR MUTE 2003/5 ...
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... PS1-0: Output Master Clock Select (see Table 4, 8) Default: “00” (256fs) PLL1-0: Input Master Clock Select at PLL Mode (see Table 2) Default: “00” (12.288MHz) MS0198-E- PLL1 PLL0 PS1 PS0 R/W R/W R/W R [AK4538 MCKO BF DIF1 DIF0 R/W R/W R/W R 2003/5 ...
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... HPRM R/W R/W R/W R Register bit PMHPR HPL HPR [AK4538 HPLM HPM LOOP SPPS R/W R/W R/W R HPM HPLM HPRM 2003/5 ...
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... TM1-0: Soft Mute Time Select (see Table 26) Default: “00” (1024/fs) TM1 MS0198-E- TM1 TM0 SMUTE DATTC R/W R/W R/W R TM0 Cycle 0 0 1024/fs Default 0 1 512/ 256/ 128/fs Table 26. Soft Mute Time Setting - 50 - [AK4538 BST1 BST0 DEM1 DEM0 R/W R/W R/W R 2003/5 ...
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... MPWRI: Power Supply Control for Internal Microphone 0: OFF (Default MPWRE: Power Supply for External Microphone 0: OFF (Default AUXAD: Switch Control from AUX IN to ADC. 0: OFF (Default MS0198-E- AUXAD MPWRE RD R/W R [AK4538 MPWRI MICAD MSEL MGAIN R/W R/W R/W R 2003/5 ...
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... Zero Crossing Timeout Period 8kHz 16kHz 128/fs 16ms 8ms 256/fs 32ms 16ms 512/fs 64ms 32ms 1024/fs 128ms 64ms Table 29. Zero Crossing Timeout Period - 52 - [AK4538 WTM1 WTM0 LTM1 LTM0 R/W R/W R/W R 44.1kHz Default ...
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... ALC1 Recovery Waiting Counter Reset Level 6.0dBFS ADC Input 4.0dBFS ADC Input RATT GAIN STEP 0 1 Default 1 2 LMAT0 ATT STEP 0 1 Default Table 32. ALC1 Limiter ATT Step Setting - 53 - [AK4538 LMAT1 LMAT0 RATT LMTH R/W R/W R/W R 8.0dBFS Default 6.0dBFS 2003/5 ...
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... IPGA does not change to 2FH + 2step = 31H, and keeps 30H. Default is “36H”. DATA (HEX Table 33. Setting Reference Value at ALC1 Recovery Operation MS0198-E- REF6 REF5 REF4 RD R/W R/W R GAIN (dB) STEP +27.5 +27.0 +26.5 : +19.0 : +0.0 : 0.5dB 5.0 5.5 6.0 6.5 7.0 7.5 8 [AK4538 REF3 REF2 REF1 REF0 R/W R/W R/W R Default 2003/5 ...
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... GAIN (dB) STEP +27.5 +27.0 +26.5 : +19.0 : +0.0 : 0.5dB 5.0 5.5 6.0 6.5 7.0 7.5 8.0 Table 34. Input Gain Setting ATTL6 ATTL5 ATTL4 ATTR6 ATTR5 ATTR4 R/W R/W R/W R [AK4538 IPGA3 IPGA2 IPGA1 IPGA0 R/W R/W R/W R Default ATTL3 ATTL2 ATTL1 ATTL0 ATTR3 ATTR2 ATTR1 ATTR0 R/W R/W R/W R 2003/5 ...
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... Microphone is not detected.(Default) 1: Microphone is detected. MS0198-E- ATTS2 ATTS1 ATTS0 RD R/W R/W R [AK4538 GN3 GN2 GN1 GN0 R/W R/W R/W R DTMIC 2003/5 ...
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... ASAHI KASEI Figure 46 shows the system connection diagram for the 52-pin QFN version of the AK4538. An evaluation board [AKD4538] is available which demonstrates the optimum layout, power supply arrangements and measurement results MICOUT 2 MDT 1 3 EXT 2.2k 4 MPE 2.2k 5 MPI 1 6 INT 7 VCOM 0.1 2.2 8 AVSS ...
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... The Mic and Beep inputs are single-ended. The input signal range scales with nominally at 0.06 x AVDD Vpp for the Mic input and 0.6 x AVDD Vpp for the Beep input, centered around the internal common voltage (0.45 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency (1/2 RC). The AK4538 can accept input voltages from AVSS to AVDD. ...
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... Power Supply (2) PDN pin = “L” “H” “L” time of 150ns or more is needed to reset the AK4538. (3) Power up VCOM : PMVCM bit = “0” VCOM should first be powered up before the other block operates. (4) Set up register 02H : MOUT2 bit = ALCS bit = “0” ...
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... Figure 48. Clock Set Up Sequence(1) “0” and power-up the X’tal oscillator: PMXTL bit = “1” “1” [AK4538 ...
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... Figure 49. Clock Set Up Sequence(2) “0” and and power-up the X’tal oscillator: PMXTL “1” “1” and set up MCKO output frequency (PS1-0 bits [AK4538 “ ...
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... Figure 50. Clock Set Up Sequence(3) “0” “1” “1”. “1” [AK4538 Data ...
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... BICK frequency at Master Mode : 64fs Input Master Clock Frequency : 256fs O utput Master Clock Frequency : 64fs XX Input Input Output Figure 52. Clock Set Up Sequence(5) “0” [AK4538 (1) Addr Data:00H (2) Input external MCLK (3) Addr Data 20H (4) Addr Data 6AH 2 S (1) Addr:01H, Data:00H ...
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... Registers set-up sequence at the ALC1 operation.” At first, clocks should be supplied according to “Clock Set Up” sequence. (1) Set up a sampling frequency (FS2-0 bits). When the AK4538 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. ...
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... If the power supply is powered off [AK4538] X ’ “ 1 ” lt ...
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... Hi-Z Figure 55. Speaker-Amp Output Sequence “1” “0” [AK4538 ’ “ 1 ” ...
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... Figure 57. Stop of Clock Sequence(2) “0” “0”, MCKPD = “0” [AK4538 ...
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... Stop an external MCLK n Power down Power down VCOM(PMVCM= “1” AK4538 is also powered-down by PDN pin = “L”. When PDN pin = “L”, the registers are initialized. MS0198-E- I ...
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... Note) The part of black at four corners on reverse side must not be soldered and must be open. n Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0198-E-01 PACKAGE 0.60 + 0. C0.6 45° Epoxy Cu Solder plate (Pb free [AK4538] 0.20 + 0. 45° 0.40 0.18 ± 0.05 0.05 M 2003/5 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0198-E-01 MARKING AKM AK4538VN XXXXXXX 1 Date code identifier (7 digits) IMPORTANT NOTICE - 70 - [AK4538] 2003/5 ...