ak4562 AKM Semiconductor, Inc., ak4562 Datasheet - Page 14

• Manufacturer Part Number: ak4562
• Description: Low Power 20bit Codec With Pga
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0031-E-00
ADC Internal
Power Supply
DAC Internal
SDTI
AOUT1
Control register
W rite to register
External clocks
PDN pin
Note: See “Register Definitions” about the condition of each register.
(1). Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of a
(3). ADC output is “0” at power down.
(4). This figure shows that MUTE of IPGA is canceled during offset calibration. If MUTE of IPGA is canceled, SDTO
(5). Click noise occurs at the “
(6). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK4562 should be in the power down
AIN
SDTO
State
State
PD:
PM:
CAL:
INIT-1:
INIT-2:
Inhibit-1:
Inhibit-2:
(GD). Output signal gradually comes to settle to input signal during a group delay.
internal ADC.
outputs Idle Noise.
system application.
(PDN pin = “L” or PM2-1 bit = “0”) mode.
PDN pin may be “L” at power-up.
Initialize cycle of ADC. Offset calibration is not executed.
Initializing all control registers.
Inhibits writing to all control registers.
Power-down state. ADC is output “0”, analog output of DAC and OPGA goes floating.
Power-down state by Power Management bit. ADC is output “0”, analog output of DAC goes floating.
During offset calibration cycle. IPGA and OPGA are set MUTE state.
Enable writing to control registers except address 01H.
Inhibit-1
INIT-2
PD
Figure 11. Power up / Power down Timing Example
PD
” of PDN signal. Please mute the analog output external if the click noise influences
(5)
(6)
Inhibit-2
GD
4128/fs
CAL
“0”data
GD (1)
The clocks may be stopped.
(4)
- 14 -
Normal
Normal
GD (1)
Idle Noise
Normal
Normal
GD (1)
(2)
(3) “0”data
(5)
“0”data
PM
PM
(6)
INIT-1
4128/fs
GD (1)
Normal
Normal
(1)
[AK4562]
2000/05
GD