ak4528 AKM Semiconductor, Inc., ak4528 Datasheet - Page 20

• Manufacturer Part Number: ak4528
• Description: High Performance 24bit 96khz Audio Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
MS0011-E-01
Addr
Addr
00H
01H
Register Definitions
PWDA: DAC power down
PWAD: ADC power down
PWVR: Vref power down
TE7-4: Test Control Register Enable
RSTDAN: DAC reset
RSTDAN: ADC reset
0: Power down
1: Power up
0: Power down
1: Power up
0: Power down
1: Power up
0: Reset
1: Normal Operation
0: Reset
1: Normal Operation
Register Name
Power Down Control
Register Name
Reset Control
Only DAC section is powered down by “0” and then the AOUTs go Hi-Z immediately. The OATTs also go
“00H”. But the contents of all register are not initialized and enabled to write to the registers.
After exiting the power down mode, the OATTs fade in the setting value of the control register (04H &
05H). The analog outputs should be muted externally as some pop noise may occur when entering to and
exiting from this mode.
Only ADC section is powered down by “0” and then the SDTO goes “L” immediately. The contents of all
register are not initialized and enabled to write to the registers.
After exiting the power down mode, ADC outputs “0” during first 516 LRCK cycles.
All sections are powered down by “0” and then both ADC and DAC do not operate. The contents of all
register are not initialized and enabled to write to the registers. When PWAD and PWDA go “0” and
PWVR goes “1”, only VREF section can be powered up.
Must be fixed to “0000”.
The internal timing is reset by “0” and then the AOUTs go VCOM voltage immediately. The OATTs also
go “00H”. But the contents of all register are not initialized and enabled to write to the registers. After
exiting the power down mode, the OATTs fade in the setting value of the control register (06H & 07H). The
analog outputs should be muted externally as some pop noise may occur when entering to and exiting from
this mode.
not initialized and enabled to write to the register.
The internal timing is reset by “0” and then SDTO goes “L” immediately. But the contents of all register are
After exiting the power down mode, ADCs output “0” during first 516 LRCK cycles.
default
default
TE7
D7
D7
0
0
0
TE6
D6
0
D6
0
0
- 20 -
TE5
D5
0
D5
0
0
TE4
D4
0
D4
0
0
D3
0
0
D3
0
0
D2
0
0
PWVR
D2
1
RSTADN
D1
PWAD
0
D1
1
[AK4528]
RSTDAN
2004/01
PWDA
D0
D0
0
1