ak4529 AKM Semiconductor, Inc., ak4529 Datasheet - Page 24

• Manufacturer Part Number: ak4529
• Description: High Performance Multi-channel Audio Codec
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
n Reset Function
When RSTN = “0”, ADC and DACs are powered-down but the internal register are not initialized. The analog outputs go
to VCOM voltage, DZF1-2 pins go to “H” and SDTO pin goes to “L”. Because some click noise occurs, the analog output
should muted externally if the click noise influences system application. Figure 11 shows the power-up sequence.
Notes:
MS0082-E-00
(1) The analog part of ADC is initialized after exiting the reset state.
(2) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(3) ADC output is “0” data at the power-down state.
(4) Click noise occurs when the internal RSTN bit becomes “1”. Please mute the digital output externally if the click
(5) The analog outputs go to VCOM voltage.
(6) Click noise occurs at 4 5/fs after RSTN bit becomes “0”, and occurs at 1 2/fs after RSTN bit becomes “1”. This
(7) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode. When exiting the reset mode, “1”
(8) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 6~7/fs after RSTN bit becomes “1”.
(9) There is a delay, 4~5/fs from RSTN bit “0” to the internal RSTN bit “0”.
(GD).
noise influences system application.
noise is output even if “0” data is input.
should be written to RSTN bit after the external clocks (MCLK, BICK and LRCK) are fed.
Clock In
MCLK,LRCK,SCLK
DZF1/DZF2
DAC Internal
DAC In
DAC Out
ADC Internal
ADC In
ADC Out
RSTN bit
Internal
RSTN bit
(Digital)
(Analog)
(Analog)
(Digital)
State
State
Normal Operation
Normal Operation
GD
Figure 11. Reset sequence example
GD
(2)
(2)
Digital Block Power-down
Digital Block Power-down
(6)
(7)
4~5/fs (9)
Don’t care
“0”data
“0”data
(5)
- 24 -
(3)
(6)
1~2/fs (9)
4 5/fs (8)
Init Cycle
516/fs
(1)
Normal Operation
(4)
Normal Operation
GD
GD
[AK4529]
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