ia186eb Innovasic Semiconductor Inc., ia186eb Datasheet - Page 30

• Manufacturer Part Number: ia186eb
• Description: 8-bit/16-bit Microcontrollers
• Manufacturer: Innovasic Semiconductor Inc.

IA186EB/IA188EB
8-Bit/16-Bit Microcontrollers
Table 7. IA186EB Pin/Signal Descriptions (Continued)
resin_n
Signal
pdtmr
pereq
ready
rd_n
resin_n
Name
pdtmr
pereq
ready
rd_n
®
PLCC
36
39
18
37
4
Pin
PQFP
NA
24
73
25
6
UNCONTROLLED WHEN PRINTED OR COPIED
LQFP
NA
67
36
49
68
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IA211080314-02
power-down timer. Input/Output (push-pull).
Note: The IA186EB enters Powerdown Mode
when the PWRDN bit in the Power Control
Register is set to 1 and a HALT instruction is
executed. Exit from the Powerdown Mode
occurs upon receipt of a non-maskable interrupt
(i.e., assertion of the nmi input) or a reset (i.e.,
assertion of the resin_n input).
The pdtmr pin, which is normally connected to
an external capacitor, determines the amount of
time that the IA186EB waits before resuming
normal operation after an exit from the
Powerdown when a non-maskable interrupt is
received—essentially a delay between the
assertion of the nmi input and the enabling of
the IA186EB internal clocks. The delay
required depends on the start-up characteristics
of the crystal oscillator.
The pdtmr pin does not apply when the
Powerdown Mode is exited by the receipt of a
reset (i.e., the assertion resin_n).
numerics coprocessor external request. Input.
Active High. When asserted (high), this signal
indicates that a data transfer between an Intel
80C187 Numerics Coprocessor.and memory is
pending.
read. Output. Active Low. When asserted
(low), rd_n indicates that the accessed memory
or I/O device must drive data from the location
being accessed onto the data bus.
ready. Input. Active High. When asserted
(high) the ready line indicates a bus-cycle
completion. This signal must be active to
terminate any bus cycle unless the IA186EB
Chip-Select Unit is being used, in which case,
ready is ignored.
reset input. Input. Active Low. When resin_n
is asserted (low), the IA186EB immediately
terminates any bus cycle in progress and
assumes an initialized state. All pins are driven
to a known state, and resout (see next table
entry) is asserted.
Description
http://www.Innovasic.com
January 14, 2009
Customer Support:
Data Sheet
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