eclamp2386k Semtech Corporation, eclamp2386k Datasheet - Page 4

• Manufacturer Part Number: eclamp2386k
• Description: Esd/emi Protection For Color Lcd Interfaces
• Manufacturer: Semtech Corporation

Device Connection
The EClamp2386K is comprised of six identical circuits
each consisting of a low pass filter for EMI/RFI sup-
pression and dual TVS diodes for ESD protection. The
device is in a 12-pin SLP package. Electrical connec-
tion is made to the 12 pins located at the bottom of
the device. A center tab serves as the ground connec-
tion. The device has a flow through design for easy
layout. Pin connections are noted in Figure 1. All path
lengths should be kept as short as possible to minimize
the effects of parasitic inductance in the board traces.
Recommendations for the ground connection are given
below.
Ground Connection Recommendation
Parasitic inductance present in the board layout will
affect the filtering performance of the device. As
frequency increases, the effect of the inductance
becomes more dominant. This effect is given by
Equation 1.
Where:
L= Inductance (H)
f = Frequency (Hz)
Via connections to the ground plane form rectangular
wire loops or ground loop inductance as shown in
Figure 2. Ground loop inductance can be reduced by
using multiple vias to make the connection to the
ground plane. Bringing the ground plane closer to the
signal layer (preferably the next layer) also reduces
ground loop inductance. Multiple vias in the device
ground pad will result in a lower inductive ground loop
over two exterior vias. Vias with a diameter d are
separated by a distance y run between layers sepa-
rated by a distance x. The inductance of the loop path
is given by Equation 2. Thus, decreasing distance x
and y will reduce the loop inductance and result in
better high frequency filter characteristics.
XLF
PROTECTION PRODUCTS
© 2007 Semtech Corp.
Equation 1: The Impedance of an Inductor at
(
, L
) f
=
2
*
π
f *
Frequency XLF
*
L
4
Where:
d = Diameter of the wire (in)
x = Length of wire loop (in)
y = Breath of wire loop (in)
LRECT
Equation 2: Inductance of Rectangular Wire Loop
Figure 2 - Inductance of Rectangular Wire Loops
Figure 1 - Pin Identification and Configuration
C
(
Ground
Ground
Via 1
Via 1
e
, d
7
t n
1
P
, x
-
r e
-
n i
In 1
In 2
In 3
In 4
In 5
In 6
1
6
) y
2
T
b a
x
x
=
y
y
10
(Top Side View)
1
6
.
16
Ground
Ground
Via 2
Via 2
GND
*
d
d
10
−
EClamp2386K
d I
O
9
n I
12
7
u
*
e
p
n
p t
r G
[
t u
x
f i t
Ground Layer
Ground Layer
Layer
Layer
t u
u o
Out 1
Out 2
Out 3
Out 4
Out 5
Out 6
*
c i
Signal Layer
Signal Layer
L
n
ln
L
PRELIMINARY
t a
n i
n i
d
[ ]
o i
s e
s e
2
www.semtech.com
y *
d
n
+
y
*
ln
[ ]
2
x *
d
]