as5510 austriamicrosystems, as5510 Datasheet - Page 9

• Manufacturer Part Number: as5510
• Description: Linear Hall Sensor With I 2 C Output
• Manufacturer: austriamicrosystems

AS5510
Data Sheet
8.2
The AS5510 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a
device receiving data as a receiver. The device that controls the message is called a master. The devices that are
controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls
the bus access and generates the START and STOP conditions must control the bus. The AS5510 operates as a
slave on the I²C bus. Within the bus specifications a standard mode (100 kHz maximum clock rate) a fast mode
(400 kHz maximum clock rate) and fast mode plus (1MHz maximum clock rate) are defined. The AS5510 works in
all three modes. Connections to the bus are made through the open-drain I/O lines SDA and the input SCL. Clock
stretching is not included.
The following bus protocol has been defined:
Accordingly, the following bus conditions have been defined:
Bus Not Busy
Both data and clock lines remain HIGH.
Start Data Transfer
A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.
Stop Data Transfer
A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.
Data Valid
The state of the data line represents valid data when, after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the
clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions are not limited, and are determined by the master device.
The information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Acknowledge
Each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte.
The master device must generate an extra clock pulse that is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that
the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. A master must signal an end of READ access to the slave by not generating
an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the
data line HIGH to enable the master to generate the STOP condition.
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I²C Modes
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the
data line while the clock line is HIGH are interpreted as start or stop signals.
Revision 1.25
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