adf7012 Analog Devices, Inc., adf7012 Datasheet - Page 20

• Manufacturer Part Number: adf7012
• Description: Multichannel Ism Band Fsk/gfsk/ook/gook/ask Transmitter
• Manufacturer: Analog Devices, Inc.

ADF7012
315 MHZ OPERATION
The recommendations here are guidelines only. The design
should be subject to internal testing prior to FCC site testing.
Matching components need to be adjusted for board layout.
The FCC standard 15.231 regulates operation in the band
from 260MHz to 470MHz in the US. This is used generally in
the transmission of RF control signals, such as in a satellite-
decoder remote control, or remote keyless entry system. The
band cannot be used to send any continuous signal. The
maximum output power allowed is governed by the duty cycle
of the system. A typical design example for a remote control is
shown next.
Design Criteria
315 MHz center frequency
FSK/OOK modulation
1 mW output power
House range
Meets FCC 15.231
The main requirements in the design of this remote are a long
battery life and sufficient range. It is possible to adjust the
output power of the ADF7012 to increase the range depending
on the antenna performance.
The center frequency is 315 MHz. Because the ADF7012
VCO is not recommended for operation in fundamental mode
for frequencies below 400 MHz, the VCO needs to operate at
630 MHz. Figure 36 (Output Frequency vs. External Inductor
Value) implies an inductor value of 7.6 nH or close to this. The
chip inductor chosen = 7.5 nH (0402CS-7N5 from Coilcraft).
Coil inductors are recommended to provide sufficient Q for
oscillation.
Crystal and PFD
Phase noise requirements are not excessive as the adjacent
channel power requirement is −20 dB. The PFD is chosen so as
to minimize spurious levels (beat note and reference), and to
ensure a quick crystal power-up time.
PFD = 3.6864 MHz − Power-Up Time 1.6ms. Figure 10 shows a
typical power-on time for a 4 MHz crystal.
N-Divider
The N Divider is determined as being:
Deviation
The deviation is set to ± 50 kHz so as to accommodate a simple
receiver architecture.
The modulation steps available are in 3.6864 MHz/2
Nint = 85
Nfrac = (1850)/4096
VCO divide-by-2 is enabled
Modulation steps = 225 Hz
Modulation number = 50 kHz/225 Hz = 222
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Bias Current
Because low current is desired, a 2.0 mA VCO bias can be used.
Additional bias current reduces any spur, but increases current
consumption.
The PA bias can be set to 5.5 mA and achieve 0 dBm.
Loop Filter Bandwidth
The loop filter is designed with ADIsimPLL Version 2.5. The
loop bandwidth design is straightforward because the 20 dB
bandwidth is generally of the order of >400 kHz (0.25% of
center frequency). A loop bandwidth of close to 100 kHz strikes
a good balance between lock time and spurious suppression. If
it is found that pulling of the VCO is more than desired in OOK
mode, the bandwidth could be increased.
Design of Harmonic Filter
The main requirement of the harmonic filter should ensure that
the third harmonic level is < −41.5 dBm. A fifth-order
Chebyshev filter is recommended to achieve this, and a
suggested starting point is given next. The Pi format is chosen
to minimize the more expensive inductors.
Component Values—Crystal: 3.6864MHz
Loop Filter
I
LBW
C1
C2
C3
R1
R2
Matching
L1
L2
C14
C15
Harmonic Filter
L4
L5
CF1
CF2
CF3
CP
0.866 mA
100 kHz
680 pF
12 nF
220 pF
1.1 kV
3 kV
56 nH
1 nF
Short
Open
22 nH
22 nH
3.3 pF
8.2 pF
3.3 pF