pc1600cl Infineon Technologies Corporation, pc1600cl Datasheet
pc1600cl
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Edition 2004-01 Published by Infineon Technologies AG, St.-Martin-Strasse 53, Edition 2004-01 81669 München, Germany Published by Infineon Technologies AG, Infineon Technologies AG 2004. © St.-Martin-Strasse 53, All Rights Reserved. 81669 München, Germany Attention please! Infineon Technologies AG 2004. © All ...
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– – B HYS72D64500GR–[7F/7/8]–B HYS72D1285[20/21]GR–[7F/7]– – ...
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HYS72D32500GR–[7F/7/8]–B, HYS72D64500GR–[7F/7/8]–B, HYS72D1285[20/21]GR–[7F/7]–B Revision History: Rev. 1.03 Previous Version: V.092 Page Subjects (major changes since last revision) all Editorial changes We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview 1.1 Features • 184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for “1U” PC, Workstation and Server main memory applications • One rank 32M 72, 64M 72 and two ranks 128M • JEDEC standard Double Data Rate Synchronous DRAMs ...
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Table 2 Ordering Information Product Type Compliance Code PC2100 (CL = 2): HYS72D32500GR-7F-B PC2100R-20220-L HYS72D32500GR-7-B PC2100R-20330-L HYS72D64500GR-7F-B PC2100R-20220-M HYS72D64500GR-7-B PC2100R-20330-M HYS72D128520GR-7F-B PC2100R-20220-N HYS72D128520GR-7-B PC2100R-20330-N HYS72D128521GR-7F-B PC2100R-20220-N HYS72D128521GR-7-B PC2100R-20330-N PC1600 (CL = 2): HYS72D32500GR-8-B PC1600R-20220-L HYS72D64500GR-8-B PC1600R-20220-M HYS72D128521GR-8-B PC1600R-20220-M Note: All ...
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Pin Configuration Table 3 Pin Definitions and Functions Symbol Type A0 – A11, A12 Input BA0, BA1 Input DQ0 – DQ63 Input/Output CB0 – CB7 Input/Output RAS Input CAS Input WE Input CKE0, CKE1 Input DQS0 – DQS8 Input/Output ...
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Table 4 Address Format Density Organization Memory Ranks 256 MB 32M 512 MB 64M 128M 72 2 Table 5 Pin Configuration PIN# Symbol PIN REF 2 DQ0 ...
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Table 5 Pin Configuration (cont’d) PIN# Symbol PIN# 31 DQ19 DQ24 DQ25 81 36 DQS3 DQ26 85 40 DQ27 86 ...
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RS0 DQS0 DM0/DQS9 S DM DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 I/O 4 DQ4 I/O 5 DQ5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DM1/DQS10 DM S I/O 0 DQ8 I/O 1 DQ9 ...
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VSS RS0 DQS0 DQS S DM I/O 0 DQ0 I/O 1 DQ1 D0 I/O 2 DQ2 I/O 3 DQ3 DQS1 DQS S DM I/O 0 DQ8 I/O 1 DQ9 D1 I/O 2 DQ10 I/O 3 DQ11 DQS2 DQS S DM ...
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V SS RS1 RS0 DQS0 DQS S DM I/O 0 DQ0 I/O 1 DQ1 D0 I/O 2 DQ2 DQ3 I/O 3 DQS1 DQS DM S I/O 0 DQ8 I/O 1 DQ9 D1 I/O 2 DQ10 I/O 3 DQ11 DQS2 DQS ...
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Electrical Characteristics 3.1 Operating Conditions Table 6 Absolute Maximum Ratings Parameter V Input/Output voltage relative Power supply voltage DDQ Storage temperature range Power dissipation (per SDRAM component) Data out current (short circuit) ...
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Current Specification and Conditions I Table 9 Conditions DD Parameter Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current ...
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Table 10 I Specifications –7F/–7 DD 256 MB 512 MB 1 GByte 1 GByte 256 MB 512 MB 1 GByte 1 GByte Rank 1 Rank 2 Ranks 2 Ranks 1 Rank –7F –7F –7F max. max. ...
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Table 11 I Specifications –8 DD 256 Rank –8 max. I 810 DD0 I 900 DD1 I 63 DD2P I 315 DD2F I 198 DD2Q I 144 DD3P I 405 DD3N I 855 DD4R I 945 DD4W ...
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AC Characteristics Table 12 AC Timing - Absolute Specifications –8/–7/-7F Parameter Symbol t DQ output access time from AC CK/CK t DQS output access time from DQSCK CK/CK CK high-level width low-level width t CL Clock ...
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Table 12 AC Timing - Absolute Specifications –8/–7/-7F Parameter Symbol t Address and control input setup IS time Address and control input hold t IH time Read preamble t RPRE t Read preamble setup time RPRES t Read postamble RPST ...
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The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the ...
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SPD Contents Table 13 SPD Codes for HYS72D32500GR–[7F/7/8]-B Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in E2PROM 1 Total number of Bytes in E2PROM 2 Memory Type (DDR = 07h) 3 Number of Row Addresses ...
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Table 13 SPD Codes for HYS72D32500GR–[7F/7/8]-B Label Code Jedec SPD Revision Byte# Description 26 tAC SDRAM @ CLmax -1 [ns] 27 tRPmin [ns] 28 tRRDmin [ns] 29 tRCDmin [ns] 30 tRASmin [ns] 31 Module Density per Rank 32 tAS, tCS ...
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Table 13 SPD Codes for HYS72D32500GR–[7F/7/8]-B Label Code Jedec SPD Revision Byte# Description 70 JEDEC ID Code of Infineon (7) 71 JEDEC ID Code of Infineon (8) 72 Module Manufacturer Location 73 Part Number, Char 1 74 Part Number, Char ...
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Table 13 SPD Codes for HYS72D32500GR–[7F/7/8]-B Label Code Jedec SPD Revision Byte# Description 97 Module Serial Number (3) 98 Module Serial Number (4) 99-127 not used Table 14 SPD Codes for HYS72D64500GR–[7F/7/8]–B Label Code Jedec SPD Revision Byte# Description 0 ...
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Table 14 SPD Codes for HYS72D64500GR–[7F/7/8]–B Label Code Jedec SPD Revision Byte# Description 6 Data Width (LSB) 7 Data Width (MSB) 8 Interface Voltage Levels 9 tCK @ CLmax (Byte 18) [ns] 10 tAC SDRAM @ CLmax (Byte 18) [ns] ...
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Table 14 SPD Codes for HYS72D64500GR–[7F/7/8]–B Label Code Jedec SPD Revision Byte# Description 33 tAH, TCH [ns] 34 tDS [ns] 35 tDH [ns] 36-40 not used 41 tRCmin [ns] 42 tRFCmin [ns] 43 tCKmax [ns] 44 tDQSQmax [ns] 45 tQHSmax ...
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Table 14 SPD Codes for HYS72D64500GR–[7F/7/8]–B Label Code Jedec SPD Revision Byte# Description 77 Part Number, Char 5 78 Part Number, Char 6 79 Part Number, Char 7 80 Part Number, Char 8 81 Part Number, Char 9 82 Part ...
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Table 15 SPD Codes for HYS72D1285[20/21]GR[–7F/7]–B, HYS72D128521GR–8 Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in E2PROM 1 Total number of Bytes in E2PROM 2 Memory Type (DDR = 07h) 3 Number of Row Addresses 4 Number ...
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Table 15 SPD Codes for HYS72D1285[20/21]GR[–7F/7]–B, HYS72D128521GR–8 Label Code Jedec SPD Revision Byte# Description 27 tRPmin [ns] 28 tRRDmin [ns] 29 tRCDmin [ns] 30 tRASmin [ns] 31 Module Density per Rank 32 tAS, tCS [ns] 33 tAH, TCH [ns] 34 ...
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Table 15 SPD Codes for HYS72D1285[20/21]GR[–7F/7]–B, HYS72D128521GR–8 Label Code Jedec SPD Revision Byte# Description 67 JEDEC ID Code of Infineon (4) 68 JEDEC ID Code of Infineon (5) 69 JEDEC ID Code of Infineon (6) 70 JEDEC ID Code of ...
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Table 15 SPD Codes for HYS72D1285[20/21]GR[–7F/7]–B, HYS72D128521GR–8 Label Code Jedec SPD Revision Byte# Description 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99- ...
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Package Outlines 1 2.5 ±0.1 ø0 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 4 Package Outlines Raw Card L (L-DIM-184-13) Data Sheet HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B ...
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64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 5 Package Outlines Raw Card M (L-DIM-184-12) Data Sheet HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B Registered DDR SDRAM-Modules ...
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64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 6 Package Outlines Raw Card N (L-DIM-184-14) Data Sheet HYS72D[128/64/32]5[00/20/21]GR–[7F/7/8]-B Registered DDR SDRAM-Modules ...
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Application Note Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during ...
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Power-Up Sequence with RESET — Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on ...
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SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT). The deactivate time defines the time in which the clocks and the control and address signals must maintain ...
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Self Refresh Exit (RESET low, clocks running) — Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should ...
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Published by Infineon Technologies AG ...