ipm6220a Intersil Corporation, ipm6220a Datasheet - Page 9

• Manufacturer Part Number: ipm6220a
• Description: Advanced Triple Pwm And Dual Linear Power Controller For Portable Applications
• Manufacturer: Intersil Corporation

3.3V Main and 5V Main Soft Start, Sequencing and
Stand-by
See Table 1 for the output voltage control algorithm. The 5V
Main and 3.3V Main converters are enabled if SDWN1 and
SDWN2 are high and SDWNALL is also high. The stand-by
mode is defined as a condition when SDWN1 and SDWN2 are
low and the PWM converters are disabled but SDWNALL is
high (3.3V ALWAYS and 5V ALWAYS outputs are enabled). In
this power saving mode, only the low power micro-controller
and keyboard may be powered.
Soft start of the 3.3V Main and 5V Main converters is
accomplished by means of capacitors connected from pins
SDWN1 and SDWN2 to ground. In conjunction with 5PA
internal current sources, they provide a controlled rise of the
3.3V Main and 5V Main output voltages. The value of the
soft-start capacitors can be calculated from the following
expression.
Where Tss is the desired soft-start time.
By varying the values of the soft-start capacitors, it is possible
to provide sequencing of the main outputs at startup.
Figure 7 shows the soft-start initiated by the SDWNALL pin
being pulled high with the Vbatt input at 10.8V and the
resulting 3.3V Main and 5V Main outputs.
Css
SDWNALL SDWN1
0
1
1
1
1
=
5PA
--------------------------- -
3.5V
TABLE 1. OUTPUT VOLTAGE CONTROL
u
Tss
X
0
1
0
1
SDWN2
X
0
0
1
1
9
3V AND 5V
ALWAYS
OFF
ON
ON
ON
ON
5V MAIN 3V MAIN
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
ON
ON
IPM6220A
While the SDWNALL pin is held low, prior to T0, all outputs
are off. Pulling SDWNALL high enables the 3.3V ALWAYS
and 5V ALWAYS outputs. With the 3.3V Main and 5V Main
outputs enabled, at T1, the internal 5PA current sources start
charging the soft start capacitors on the SDWN1 and
SDWN2 pins. At T2 the outputs begin to rise and because
they both have the same value of soft-start capacitors,
0.022PF, they both reach regulation at the same time, T3.
The soft-start capacitors continue to charge and are
completely charged at T4.
12V Converter Architecture
The 12V boost converter generates its output voltage from
the 5V Main output. An external MOSFET, inductor, diode
and capacitor are required to complete the circuit. The
output signal is fed back to the controller via an external
resistive divider. The boost controller can be disabled by
connecting the VSEN3 pin to 5V ALWAYS.
The control circuit for the 12V converter consists of a 3:1
frequency divider which drives a ramp generator and resets
a PWM latch as shown in Figure 8. The width of the CLK/3
pulses is equal to the period of the main clock, limiting the
duty cycle to 33%. The output of a non-inverting error
amplifier is compared with the rising ramp voltage. When the
ramp voltage becomes higher than the error signal, the
PWM comparator sets the latch and the output of the gate
driver is pulled high providing leading edge, voltage mode
PWM. The falling edge of the CLK/3 pulses resets the latch
and pulls the output of the gate driver low.
0V
0V
FIGURE 7. SOFT-START ON 3.3V AND 5V OUTPUTS
SDWN2, 2V/DIV.
T0 T1
V
SDWN1, 2V/DIV.
IN
SDWNALL,10V/DIV.
= 10.8V
T2
5V
OUT
4ms/DIV.
, 2V/DIV.
3.3V
T3
OUT
T4
, 2V/DIV.