hsp50307 Intersil Corporation, hsp50307 Datasheet - Page 4

• Manufacturer Part Number: hsp50307
• Description: Burst Qpsk Modulator
• Manufacturer: Intersil Corporation

Control Interface
The QPSK modulator is configured via a serial three wire
interface. When C_EN is high, 23 bits are shifted in at the
CDATA pin on the falling edge of CCLK. Figure 3 shows the
timing diagram for loading the serial configuration data.
Table 1 describes the 23-bit serial configuration data. See
the Synthesizer Section for more details on the frequency
control bits.
TABLE 1. 23-BIT SERIAL DATA CONTROL INTERFACE
NOTE: D0 is the first bit shifted into the part.
D0-D2
(Note)
D3-D9
D10
D11
D12
D13-D18
D19-D21
D22
POSITION
C_DATA
CCLK
BIT
C_EN
DESCRIPTION
Synthesizer
Control Bits
Synthesizer
Control Bits
Synthesizer
Enable
Charge Pump
Current
Control
Three-State
Control
Attenuation
Control
Reserved
DSP Shut
Down
FUNCTION
D22
Pre-scaler control register.
A = (0 to 5), D2 is the MSB.
Feedback Counter Control Register.
M = (41 to 103) D9 is the MSB.
Active high. This bit activates chip bias
networks for normal operation. D10 = 0
places part in low power mode.
D11 = 0 sets charge pump current to
500 A.
D11 = 1 sets charge pump current to
1mA.
D12 = 0 three-states the charge pump
output when a pump up and down
command
D12 = 1 disables three-state.
Controls output power level. The bina-
ry value of the register corresponds to
an attenuation amount. For example,
000100 corresponds to 4dB attenua-
tion from the maximum 62dBmV level.
D18 is the MSB.
Used for test/diagnostic purposes.
Set to 000.
Test mode; D22 = 0 sets the burst
QPSK modulator in normal mode.
D22 = 1 disables the digital filter.
D21
DESCRIPTION
FIGURE 3. CONTROL INTERFACE TIMING DIAGRAM
t
CDS
occur
t
CCH
simultaneously.
D20
HSP50307
t
CDH
D19
7-71
Synthesizer
The synthesizer generates the quadrature LO’s for
modulating the baseband data to RF. The carrier frequency
is phase locked to the reference clock (RCLK). The carrier
frequency, F
with a resolution of 32kHz. Equation 1 gives the relationship
between F
control bits, M and A.
where F
can be determined by
“A” ranges from 0 to 5 and “M” ranges from 41 to 103. A and
M are programmed via control bits D0-D2 and D3-D9,
respectively. Values outside these ranges are invalid.
I/Q Generator
The I/Q Generator Section demultiplexes and time aligns the
256 KBPS input data into two data streams, I and Q. The
first data bit following the assertion of the TX_EN signal is
the I data of the first I/Q pair. Each I/Q pair determines the
phase angle of the QPSK transmission signal. The relation-
ship between I/Q pairs and phase angles is shown in
Table 2. Since the QPSK encoding requires a pair of I and Q
information to transmit one symbol, an even number of data
bits must be provided for each burst.
F
M
C
+
=
A
--- -
6
6 M
-------------------------------- - F
=
D3
REF
0
0
1
1
I
+
64
----- -
64
6
C
1
C
and the frequency of RCLK and the frequency
equals the frequency of RCLK. Also, M and A
+
, has a frequency range of 8MHz to 15MHz
-------------- -
F
A
F
REF
TABLE 2. QPSK ENCODING
C
REF
D2
–
1.
,
Q
0
1
0
1
D1
D0
PHASE
-135
135
-45
45
o
o
o
o
(EQ. 1)
(EQ. 2)