hsp50214a Intersil Corporation, hsp50214a Datasheet - Page 40
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hsp50214a
Manufacturer Part Number
hsp50214a
Description
Programmable Downconverter
Manufacturer
Intersil Corporation
Datasheet
1.HSP50214A.pdf
(60 pages)
- Current page: 40 of 60
- Download datasheet (528Kb)
CONTROL
WORD 23
A(2:0)
DATA
NEW
RD
|r|
Q
I
SEQUENCER
WRITE
16
16
16
16
16
ADDRESS “5”
0: I;Q
1: |r|;
2:
4: INPUT AGC
5: AGC; TIMING
(R/ SELECTED)
(I/Q SELECTED)
WRITE
FIGURE 41. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM
WRITES TO
SNAPSHOT
PROCCLK
DATARDY
DATARDY
INTRRPT
“SET OF WORDS”
INCR
WR
RAM
SEQUENCER
ADDRESS
DUAL
PORT
R2, R1, R0
A2, A1, A0
RAM
INCR
RD
I/Q
STATUS
INT(22:16)
I
Q
|r|
INT(15:0)
R/
DELAY TO DATARDY DEPENDS ON LENGTH OF FIR IF FREQ CHOSEN
I
TIMING
AGC
0
1
2
3
4
R1
FIGURE 42. RAM LOAD SEQUENCE
Q
R0
0
1
2
3
A1
0
R0 A1
1
R
HSP50214A
A0
R2
MSByte
LSByte
40
0
1
A2
0
1
A1
A0
OUTPUT
DATA
R2 R1 R0 A2 A1 A0 SELECTION
X
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
X
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
1
1
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
X
X
0
0
1
1
0
0
1
1
0
0
0
0
1
0
0
1
1
1
X NOT USED
X NOT USED
0 RAM I LSB
1 RAM I MSB
0 RAM Q LSB
1 RAM Q MSB
0 RAM |r| LSB
1 RAM |r| MSB
0 RAM
1 RAM
0 RAM
1 RAM
0 INPUT INTEG LSB
1 INPUT INTEG NMSB
0 INPUT INTEG MSB
0 AGC LSB
1 AGC MSB
0 TIMING LSB
1 TIMING MSB
1 STATUS
LSB
MSB
LSB
MSB
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