hsp50214 Intersil Corporation, hsp50214 Datasheet
hsp50214
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hsp50214 Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 321-724-7143 Copyright Description The HSP50214 Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable conversion, decimation, narrowband low pass filtering, gain scaling, re-sampling, and Cartesian to Polar coordinate conversion ...
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... CC 16 CLKIN GND ENI GAINADJ2 20 GAINADJ1 21 GAINADJ0 22 COF 23 COFSYNC 24 GND 25 26 SOF 27 SOFSYNC SYNCIN1 30 SYNCIN2 HSP50214 120 LEAD MQFP TOP VIEW 2 90 DATARDY 89 OEBH 88 BOUT15 87 BOUT14 BOUT13 84 BOUT12 83 BOUT11 82 BOUT10 81 BOUT9 80 BOUT8 79 GND 78 77 GND ...
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... AOUT(15:0) O Parallel Output Bus A. Two parallel output sources are available on the HSP50214. The first is called the Direct Output Port, where the source is selected through control word 20 (see the Microprocessor Write section) and comes directly from the Output MUX section (see Output Control Section). The most signifi ...
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... Multiple Chip Sync Output. Provided for synchronizing multiple parts when CLKIN and PROCCLK are asynchronous. MSYNCO is the synchronization signal between the input section operating under CLKIN and the back end processing operating under PROCCLK. This output sync signal from one part is connected to the MSYNCI signal of all the HSP50214s. MSYNCI I Multiple Chip Sync Input ...
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... PROCESSOR INTERFACE COF NCO COFSYNC (CARRIER TRACKING) SOF SOFSYNC REFCLK MICROPROCESSOR READ/WRITE RD WR CONTROL A(2:0) SECTION C(7:0) FIGURE 1. FUNCTIONAL BLOCK DIAGRAM OF THE HSP50214 PROGRAMMABLE DOWNCONVERTER TO OUTPUT FORMATTER AGCOUT AND MICROPROCESSOR INTERFACE 255-TAP PROGRAMMABLE AGC RESAMPLER FIR FILTER (DECIMATE ...
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... Output sections. All of these sections are configured through a microprocessor interface. The HSP50214 has three clock inputs; two are required and one is optional. The input level detector, carrier NCO, and CIC decimating filter sections operate on the rising edge of the input clock, CLKIN. The halfband fi ...
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... The FM dis- criminator has a 63-tap programmable, 22-bit coefficient FIR fil- ter for additional signal conditioning of the FM signal. Digital HSP50214 versions of these formats, ASK and FSK are also readily pro- cessed using the PDC. Just as in the AM modulated case, ASK ...
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... CLKIN. B The interpolated mode allows the user to input data at a low HSP50214 sample rate and to zero-stuff the data prior to filtering. This zero stuffing effectively interpolates the input signal up to the MSO rate of the input clock (CLKIN) ...
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... CIC filter path will not yield the desired 85dB dynamic range band width of 500kHz. FIGURE 4. STATEMENT OF THE PROBLEM HSP50214 cessor interface through Control Word 1. Only the upper 16 bits are programmable. The 2 LSBs are always zero. Con- ...
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... FIGURE 7. ALIAS PROFILE AND THE 85dB DYNAMIC RANGE BANDWIDTH INPUT FIGURE 8. PROCESSOR BASED EXTERNAL IF AGC INPUT GATING IN(13:0) LOGIC † INPUT_THRESHOLD † INTEGRATION_INTERVAL † START † INTEGRATION_MODE CLKIN † Controlled via microprocessor interface. HSP50214 ...
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... Carrier Synthesizer/Mixer The carrier synthesizer/mixer section of the HSP50214 shown in Figure 12. The NCO has a 32-bit phase accumula tor, a 10-bit phase offset adder, and a sine/cosine ROM The frequency of the NCO is the sum of a center frequency ...
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... OFF where PO is the 10-bit two’s complement value loaded into the Phase Offset register (Control Word 4, bits 9-0). For example, a value of 32 (decimal) loaded into the Phase Offset register HSP50214 is 52MHz, then would produce a phase offset of 11.25 IN would produce an offset of 180 the microprocessor interface ...
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... Table 3 details the permissible values for the GAINADJ(2:0) barrel shifter control, while the Figure 15 shows the permissible CIC Shift Gain values. The CIC filter structure for the HSP50214 is fifth order; that is it has five integrator/comb pairs. A fifth order CIC has 84dB of alias attenuation for output frequencies below 1/8 the CIC output sample rate ...
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... R is the decimation factor and N is the number of stages. The input to the CIC from the mixer is 15 bits, and the bit widths of the accumulators for the five stages in the HSP50214 are 40, 36, 32, 32, and 32, as shown in Figure 16. This limits the maxi- mum decimation in the CIC to 32 for a full scale input 32, the gain through all fi ...
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... HALFBAND FILTER 5 -60 HALFBAND FILTER 4 HALFBAND FILTER 3 -80 HALFBAND FILTER 2 HALFBAND FILTER 1 -100 -120 0.125 0.25 NORMALIZED FREQUENCY (F FIGURE 18. HALFBAND FILTER FREQUENCY RESPONSE HSP50214 HALFBAND FILTER INPUT CONTROL WORD 7, BIT HB1 CONTROL WORD 7, BIT HB2 CONTROL WORD 7, BIT 17 (EQ ...
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... Equation 10 shows the minimum ratio needed. HB5 f /f ([(7)(HB5)(2 )+ PROCCLK S (HB4 + HB5) (6)(HB4)(2 )+ (HB3+HB4+HB5) (5)(HB3)(2 (HB2+HB3+ HB4+HB5) (4)(HB2)(2 (HB1+HB2+HB3+HB4+HB5) (3)(HB1)(2 HSP50214 TABLE 4. HALFBAND FILTER COEFFICIENTS HALFBAND #2 HALFBAND #3 0.005929947 -0.00130558 0.000000000 -0.000000000 -0.049036026 -0.012379646 0.000000000 -0.000000000 0.29309082 -0.06055069 0.499969482 -0.000000000 0.29309082 -0 ...
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... Control Words 128 through 255 (see Microprocessor Write Section). For real filters, the same coefficients are used by I and Q paths. If the filter is configured as a symmetric filter HSP50214 using Control Word 17 bit 9, then coefficients are loaded starting with the center coefficient in Control Word 128 and proceed to last coeffi ...
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... Figure 21 illustrates the transfer function of the AGC multi- plier versus mantissa control for Figure 22 illustrates the complete AGC Multiplier/Shifter Transfer function for all values of exponent and mantissa control. HSP50214 112 128 144 160 176 192 208 224 240 AGC CONTROL MANTISSA VALUES (TIMES 256) FIGURE 21 ...
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... The ranges and format for these limit values are shown in Tables The bit weightings for the AGC Loop Feedback elements is detailed in Table 9. CONTROL WORD 9 BIT: FORMAT HSP50214 TABLE 6A. AGC LIMIT EXPONENT vs GAIN GAIN(dB) 96.330 90.309 84.288 78 ...
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... The loop gain determines the growth rate of the sum in the loop accumulator which, in turn, determines how quickly the AGC gain traces the transfer function given in Figures 21 and 22. Since the log of the gain response is roughly linear, the loop response can be approximated by multiplying the HSP50214 (RANGE = 0 TO 2.18344 LIMIT ...
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... AGC loop. The AGC Gain select is a con- trol input to the device, selecting Gain 0 when AGCGNSEL = 0, and selecting Gain 1 when AGCGNSEL = 1. HSP50214 Resampler/Halfband Filter The Resampler is an NCO controlled polyphase filter that allows the output sample rate to have a non-integer relation- SCALE ship to the input sample rate. The fi ...
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... Input(Cart/PolarGain)(Error Det Gain)(AGC Loop Gain Max -0 AGC Response = (1)(1.64676)(2 )(1)(0.75dB) ~ 1.23dB/symbol time. Max -15 AGC Response = (1)(1.64676)(2 )(1)(0.75dB) ~ 0.00004dB/symbol time. Min Thus, the expected range for the AGC rate is ~ 0.00004 to 1.23dB/symbol time. HSP50214 AGC LOOP FILTER GAIN MULTIPLIER SHIFT SHIFT (OUTPUT ...
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... FREQUENCY (RELATIVE TO f FIGURE 24C. POLYPHASE RESAMPLER FILTER EXPANDED RESOLUTION PASSBAND FREQUENCY RESPONSE HSP50214 TABLE 10. POLYPHASE AND INTERPOLATING HALFBAND FILTER MAXIMUM CLOCKING RATES CLOCK MODE CYCLES Bypass Polyphase Filter Polyphase and 1 Halfband Filter Polyphase and 2 Halfband Filters ...
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... Number of Offset Frequency Bits (Control Word 11 bits 3-4), an Enable Offset Frequency con- trol (Control Word 11, bit 2), a Clear NCO Accumulator con- HSP50214 trol (Control Word 11, bit 1), a Timing NCO Phase Accumulator Load On Update control (Control Word 11, bit 0), the Timing NCO Center Frequency (Control Word 12), a ...
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... The magnitude conversion gain is 1.64676. The magnitude reso- lution is 16 bits. The MSB is always zero. Table 11 details the phase and magnitude weighting for the 16 bits output from the PDC. HSP50214 TABLE 11. MAG/PHASE BIT WEIGHTING BIT 15 (MSB) 14 ...
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... In the symmetric mode, the FIR can be configured for even or odd symmetry, as well as with an even or odd number of filter taps. Decimation is pro- vided to allow more processing time for longer (i.e., more taps) filter structures. HSP50214 PHASE INPUT PHASE ERROR PHASE MULTIPLIER † ...
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... NOTE: I and Q are sample aligned in time. |r| and sample is delayed in time from sample time + 63 tap FIR impulse response. If the FIR is set to decimate and fre- quencies selected for AOUT, the DATARDY signal will be at the documented rate. HSP50214 AOUT DIRECT PAR OUTPUT MODE ...
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... FIR output will be repeated every sample time until a new value appears at the filter out- put. (i.e., the frequency samples are clocked out at the I, Q sample rate regardless of decimation.) HSP50214 TABLE 13. LINKING CONTROL WORDS FOR SERIAL OUTPUT DATA TYPE IDENTIFIER ...
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... SERIAL OUTPUT CLOCK POLARITY † SERIAL OUTPUT SYNC POLARITY † Controlled via microprocessor interface ‡ Polarity is programmable FIGURE 31. SERIAL OUTPUT FORMATTER BLOCK DIAGRAM HSP50214 SEROUTB: start |r| data word > f data word > TE data word> AGC data word > end > † † ...
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... DATA WORD 3 MAGNITUDE DATA WORD 3 TBD THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE: PHASE, FREQUENCY, AGC LEVEL, AND TIMING ERROR FIGURE 32. EXAMPLE 2 SERIAL OUTPUT DATA STREAM HSP50214 SEROUTB: start Q data word > |r|data word > TBD data word> end > As shown by this example, once Q was linked to |r| in the SEROUTA chain, the SEROUTB chain must have |r| follow- ing selected ...
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... sample time + 63 tap FIR impulse response. If the FIR is set to decimate, the FIR output will be repeated every sample time until a new value appears at the filter output. (i.e., the frequency samples are clocked out at the I, Q sample rate regardless of decimation.) HSP50214 ...
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... Frequency 101 Unused 110 Memory Status 111 Reading this address increments to the next sample set HSP50214 TABLE 18. STATUS BIT DEFINITIONS AOUT BIT LOCATION (7:5) FIFO depth - When in FIFO mode, these bits are the current depth of the FIFO. 4 EMPTY - When in FIFO mode, the FIFO is empty, and the read pointer cannot be ad- vanced ...
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... Rule #2: The FIFO is full when the Write Address = Read Address -1 (no more data will be written until some samples are read or the FIFO is reset). Rule #3: The FIFO is empty when the Read Address = (Write Address -1) (the circuitry will not allow the read pointer to be incremented). HSP50214 INT RD D(15:8) 16-BIT P ...
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... INPUT AGC 5: AGC; TIMING RD FIGURE 39. 8-BIT MICROPROCESSOR INTERFACE BUFFER RAM MODE BLOCK DIAGRAM HSP50214 Recall that INTRRP stays low for 8 PROCCLK cycles. The FIFO can be read before the INTRRP signal goes low; the number of samples in the FIFO must be monitored by the user. ...
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... Care must be taken to either read sufficient data out of memory or RESET the addressing to ensure that a complete set of data is the cause of the interrupt. HSP50214 INTRRP WR A COMPLETE SET OF 3 DATA SAMPLES IS IN MEMORY AT INTRRP A: NORMAL READ/WRITE SEQUENCE ...
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... REGISTER AND WAIT 4 CLKs FIGURE 42. LOADING THE CONTROL REGISTERS WITH 32-BIT CONTROL WORDS HSP50214 Microprocessor Read Section The microprocessor read uses both read and write proce- dures to obtain data from the PDC. A write must be done to location 5 to select the source of data to be read. The read source is determined by the value placed on the lower three bits of C(7:0) ...
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... Low) (0)-INTEGRATION has been completed in the input level detector and is ready to be read. (Active High) HSP50214 Applications Composite Filter Response Example For this example consider a total receive band roughly 25MHz wide containing 124 200kHz wide FDM channels as shown in Figure 44. The design goal for the PDC is to tune to and fi ...
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... Intersil AnswerFAX (321) 724-7800. [1] HSP50210 Data Sheet, Intersil Corporation, AnswerFAX Doc. No. 3652. [2] Cellular Radio and Personal Communications: A Book of Selected Readings, Theodore S. Rappaport, 1995 by IEEE, Inc. [3] AN9720 Application Note, Intersil Corporation, “Calcu- lating Maximum Processing Rates of the PDC (HSP50214)”, AnswerFAX Doc. No. 99720. 38 ...
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... CIC INPUT RATE S -130 FREQUENCY FIGURE 46A. HB5 FILTER RESPONSE 10 -10 -30 -50 -70 -90 -110 -130 FIGURE 46C. COMPOSITE FILTER RESPONSE FIGURE 46. PDC FILTER FREQUENCY SPECTRUMS EXAMPLE (NORMALIZED TO SAME SCALE) HSP50214 10 -10 -30 -50 -70 -90 -110 f = CIC INPUT RATE S -130 f FREQUENCY S R FIGURE 45B. HB3 FILTER RESPONSE ...
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... Carrier NCO Offset Frequency Enable 0 Carrier NCO Load Phase Accum On Update HSP50214 to the master register. Figure 39 details the timing for proper operation of the Microprocessor Write Section. Bits identified as “Reserved” should be programmed to a zero. DESCRIPTION Reserved. 0- The SYNCIN1 pin has no effect on the Carrier NCO. ...
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... BIT POSITION FUNCTION N/A Carrier Phase Writing to this address updates the carrier phase offset control word with the value written to Strobe the phase offset (PO) register. HSP50214 DESCRIPTION DESCRIPTION DESCRIPTION is the input sample rate. The bits are computed by the equation DESCRIPTION ...
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... The decimal value for the mantissa is calculated as DEC(MMMM)/16. Bit 15 is the MSB. 11-8 Loop Gain 1 Selected when AGCGNSEL = 1. These bits are EEEE. See description of bits 15-12. Bit 11 is Exponent the MSB. HSP50214 DESCRIPTION DESCRIPTION -(15 - EEEE -10 down to 2 ...
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... If bit 0 of this word is set to 1, the phase accumulator feedback is also zeroed. 4-3 Number of Offset bits. Frequency Bits 32. 2 Enable Offset 0- Zero Offset Frequency to Adder. Frequency 1- Enable Offset Frequency. HSP50214 DESCRIPTION DESCRIPTION GAIN dB/20 (10 )]. 2 GAIN dB/20 eeee /2 - 1)]. GAIN dB/20 (10 )]. ...
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... POSITION FUNCTION N/A Timing Phase Strobe Writing to this address updates the active timing NCO phase offset register in the timing NCO (see Timing NCO Section). HSP50214 DESCRIPTION DESCRIPTION where F is the input sample rate to the re-sampling filter. The bits are com- RESAMP RESAMP ...
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... If ddd the decimal representation bits 2-0, then the discriminator a transfer function H(Z) = 1-Z HSP50214 DESCRIPTION puts can be delayed from 2 to 255 clocks from the first output. A delay of 2 equals 255 clocks of delay. A delay invalid mode. When interpolating by 2, one extra output is generated ...
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... The serial data word, or link, following the AGC data word is selected using Table 12 Level Data (see Output Section). 2-0 Link Following Timing The serial data word, or link, following the TIMERR data word is selected using Table 12 Error Data (see Output Section). HSP50214 DESCRIPTION DESCRIPTION 46 ...
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... I Data Serial Output Tag Selection above). Output Tag Bit 5-4 Frequency Data Se- (See I Data Serial Output Tag Selection above). rial Output Tag Bit 3-2 AGC Data Serial (See I Data Serial Output Tag Selection above). Output Tag Bit HSP50214 (SYNCHRONIZED WITH PROCCLK) DESCRIPTION ...
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... SYNCOUT Strobe A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is synchronized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on the programming of bit 3 of Control Word 0. HSP50214 DESCRIPTION DESCRIPTION 8 ), sample time counts between snapshot samples. Program ...
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... Zeros the group number. 2. Load interval counter. 3. Resets write address and read address for FIFO. Output Serial Control 1. Reloads shift counter. 2. Reloads “Number of Words” counter. 3. Reloads counter for sync (for early or late). 4. Reloads counter for dividing down SERCLK. HSP50214 DESCRIPTION 49 ...
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... The convolution starts with the oldest data, times the last complex coefficient, and ends with the newest data, times the first complex coefficient loaded. Iout Qout = (Xn-k+1_i * Ck-1_im + Xn-k+1_q * Ck-1_re). HSP50214 DESCRIPTION DESCRIPTION is loaded here for normal operation. A fixed value ...
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... CLKIN Clock Period CLKIN High CLKIN Low PROCCLK Period PROCCLK High PROCCLK Low REFCLK Clock Frequency REFCLK High HSP50214 Thermal Information Thermal Resistance (Typical, Note 1) +0.5V MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . CC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Storage Temperature Range . . . . . . . . . .-65 Maximum Lead Temperature (Soldering 10s 300 ...
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... Controlled via design or process parameters and not directly tested. Characterized upon initial design and at major process or design changes. 10. Setup time required to ensure action initiated by WR will be seen by a particular CLKIN. AC Test Load Circuit SWITCH S1 OPEN FOR I NOTE: Test head capacitance. HSP50214 5 Commercial ...
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... C(0-7), A(0-2) FIGURE 47. TIMING RELATIVE 2.0V 0.8V FIGURE 49. OUTPUT RISE AND FALL TIMES OEAH, OEAL, 1.5V OEBH, OEBL t OE OUTA(15:8), OUTA(7:0), 1.7V OUTB(15:8), OUTB(7:0) 1.3V FIGURE 51. OUTPUT ENABLE/DISABLE HSP50214 WRH A(2-0) WH C(0-7) t RDO FIGURE 48. TIMING RELATIVE TO RD IN(13:0), COF GAINADJ(2:0), ENI, COFSYNC, SYNCIN1 t RF FIGURE 50. TIMING RELATIVE TO CLKIN ...
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... For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 HSP50214 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ...