cp3cn17 National Semiconductor Corporation, cp3cn17 Datasheet - Page 87
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cp3cn17
Manufacturer Part Number
cp3cn17
Description
Reprogrammable Connectivity Processor With Can Interface
Manufacturer
National Semiconductor Corporation
Datasheet
1.CP3CN17.pdf
(220 pages)
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15.10
Table 38 lists the CAN module registers.
CSTPND
CEDIAG
CNSTAT
GMSKX
GMSKB
BMSKX
BMSKB
CANEC
CIPND
CICEN
CGCR
CICLR
CTMR
Name
CTIM
CIEN
CAN CONTROLLER REGISTERS
Table 38 CAN Controller Registers
0E F10Ch
0E F10Eh
0E F11Ah
0E F100h
0E F102h
0E F104h
0E F106h
0E F108h
0E F10Ah
0E F110h
0E F112h
0E F114h
0E F116h
0E F118h
Address
Table 37.
See
Configuration Register
Global Mask Register
Global Mask Register
CAN Timing Register
Basic Mask Register
Basic Mask Register
CAN Timer Register
CAN Interrupt Code
Diagnostic Register
CAN Buffer Status/
Pending Register
Pending Register
Counter Register
Control Register
Enable Register
Enable Register
Clear Register
CAN Interrupt
CAN Interrupt
CAN Interrupt
Description
CAN Global
CAN Status
CAN Error
CAN Error
87
15.10.1 Buffer Status/Control Register (CNSTAT)
The buffer status (ST), the buffer priority (PRI), and the data
length code (DLC) are controlled by manipulating the con-
tents of the Buffer Status/Control Register (CNSTAT). The
CPU and CAN module have access to this register.
ST
15
DLC
12 11
The Buffer Status field contains the status in-
formation of the buffer as shown in Table 39.
This field can be modified by the CAN module.
The ST0 bits acts as a buffer busy indication.
When the BUSY bit is set, any write access to
the buffer is disabled with the exception of the
lower byte of the CNSTAT register. The CAN
module sets this bit if the buffer data is cur-
rently copied from the hidden buffer or if a
message is scheduled for transmission or is
currently transmitting. The CAN module al-
ways clears this bit on a status update.
Reserved
R/W
8 7
0
PRI
4 3
www.national.com
ST
0
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