ltm4616 Linear Technology Corporation, ltm4616 Datasheet - Page 7

• Manufacturer Part Number: ltm4616
• Description: Dual 8a Per Channel Low Vin Dc/dc ?module
• Manufacturer: Linear Technology Corporation

PIN FUNCTIONS
MODE1 and MODE2 (A8 and G8): Mode Select Input for
Each Channel. Tying this pin high enables Burst Mode
operation. Tying this pin low enables forced continuous
operation. Floating this pin or tying it to V
pulse-skipping operation.
CLKIN1 and CLKIN2 (A7 and G7): External Synchroniza-
tion Input to Phase Detector for Each Channel. This pin
is internally terminated to SGND with a 50k resistor. The
phase locked loop will force the internal top power PMOS
turn on to be synchronized with the rising edge of the
CLKIN signal. Connect this pin to SV
spectrum modulation. During external synchronization,
make sure the PLLLPF pin is not tied to V
PLLLPF1 and PLLLPF2 (E6 and L6): Phase Locked Loop
Lowpass Filter for Each Channel. An internal lowpass fi lter
is tied to this pin. In spread spectrum mode, placing a
capacitor here to SGND controls the slew rate from one
frequency to the next. Alternatively, fl oating this pin allows
normal running frequency at 1.5MHz, tying this pin to SV
forces the part to run at 1.33 times its normal frequency
(2MHz), tying it to ground forces the frequency to run at
0.67 times its normal frequency (1MHz).
PHMODE1 and PHMODE2 (A9 and G9): Phase Selector
Input for Each Channel. This pin determines the phase
relationship between the internal oscillator and CLKOUT. Tie
it high for 2-phase operation, tie it low for 3-phase opera-
tion, and fl oat or tie it to V
MGN1 and MGN2 (A10 and G10): Voltage Margining Pin
for Each Channel. Tie this pin to V
ing. For margining, connect a voltage divider from V
to GND with the center point connected to the MGN pin
for the specifi c channel. Each resistor should be close to
50k. Margin High is within 0.3V of V
is within 0.3V of GND. See the Applications section and
Figure 18 for margining control. The specifi ed tri-state
drivers are capable of the high and low requirements for
margining.
BSEL1 and BSEL2 (A6 and G6): Margining Bit Select Pin
for Each Channel. Tying BSEL low selects ±5% margin
value, tying it high selects 10% margin value. Floating it
or tying it to V
TRACK1 and TRACK2 (E8 and L8): Output Voltage Track-
IN
/2 selects 15% margin value.
IN
/2 for 4-phase operation.
OUT
IN
IN
to disable margin-
, and Margin Low
to enable spread
IN
IN
or GND.
/2 enables
IN
IN
ing Pin for Each Channel. Voltage tracking is enabled
when the TRACK voltage is below 0.57V. If tracking is not
desired, then connect the TRACK pin to SV
is not tied to SV
be below 0.18V before the chip shuts down even though
RUN is already low. Do not fl oat this pin. A resistor and
capacitor can be applied to the TRACK pin to increase the
soft-start time of the regulator. TRACK1 and TRACK2 can
be tied together for parallel operation and tracking. See
the Applications section.
FB1 and FB2 (D8 and K8): The Negative Input of the Error
Amplifi er for Each Channel. Internally, this pin is connected
to V
voltages can be programmed with an additional resistor
between FB and GND pins. In PolyPhase
ing the FB pins together allows for parallel operation. See
Applications section for details.
I
Error Amplifi er Compensation Point for Each Channel. The
current comparator threshold increases with this control
voltage. Tie together in parallel operation.
I
I
SGND for single phase operation on each channel. For
PolyPhase operation, tie the master’s I
connecting all of the I
PGOOD1 and PGOOD2 (A11 and G11): Output Voltage
Power Good Indicator for Each Channel. Open-drain logic
output that is pulled to ground when the output voltage
is not within ±10% of the regulation point. Power good
is disabled during margining.
RUN1 and RUN2 (F6 and M6): Run Control Pin. A voltage
above 1.5V will turn on the module.
SW1 and SW2 (B6 and H6): Switching Node of Each
Channel That is Used for Testing Purposes. This can be
connected to copper on the board for improved thermal
performance.
CLKOUT1 and CLKOUT2 (F7 and M7): Output Clock
Signal for PolyPhase Operation. The phase of CLKOUT is
determined by the state of the PHMODE pin.
PolyPhase is a registered trademark of Linear Technology Corporation.
TH1
THM1
TH
Differential Amplifi er for Each Channel. Tie this pin to
OUT
and I
and I
with a 10kΩ precision resistor. Different output
TH2
THM2
(F8 and M8): Current Control Threshold and
IN
(E7 and L7): Negative Input to the Internal
, then the TRACK pin’s voltage needs to
THM
pins together at the master.
THM
LTM4616
®
to SGND while
operation, ty-
IN
. If TRACK
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