bs62lv1605eip70 Brillance Semiconductor, bs62lv1605eip70 Datasheet - Page 7

• Manufacturer Part Number: bs62lv1605eip70
• Description: Very Power/voltage Cmos Sram
• Manufacturer: Brillance Semiconductor

R0201-BS62LV1605
WRITE CYCLE2
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
3. T
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
6. OE is continuously low (OE = V
7. D
8. D
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
10. The parameter is guaranteed but not 100% tested.
11. T
WE
D
D
ADDRESS
CE2
CE1
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
to the outputs must not be applied.
transition, output remain in a high impedance state.
opposite phase to the outputs must not be applied to them.
IN
OUT
WR
OUT
OUT
BSI
CW
is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
is the same phase of write data of this write cycle.
is the read data of next address.
is measured from the later of CE2 going high or CE1 going low to the end of write.
(1,6)
IL
).
t
AS
(5)
t
(4,10)
WHZ
t
AW
7
t
t
t
WC
CW
WP
(11)
(2)
t
DW
t
t
t
WR
OW
DH
(3)
BS62LV1605
(8,9)
(7)
Revision 2.1
Jan.
(8)
2004